drivers/staging/rtl8723bs/include/rtl8723b_spec.h

Source file repositories/reference/linux-study-clean/drivers/staging/rtl8723bs/include/rtl8723b_spec.h

File Facts

System
Linux kernel
Corpus path
drivers/staging/rtl8723bs/include/rtl8723b_spec.h
Extension
.h
Size
8104 bytes
Lines
238
Domain
Driver Families
Bucket
drivers/staging
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __RTL8723B_SPEC_H__
#define __RTL8723B_SPEC_H__

#define HAL_NAV_UPPER_UNIT_8723B		128		/*  micro-second */

/*  */
/*  */
/*	0x0000h ~ 0x00FFh	System Configuration */
/*  */
/*  */
#define REG_RSV_CTRL_8723B				0x001C	/*  3 Byte */
#define REG_BT_WIFI_ANTENNA_SWITCH_8723B	0x0038
#define REG_HSISR_8723B					0x005c
#define REG_PAD_CTRL1_8723B		0x0064
#define REG_AFE_CTRL_4_8723B		0x0078
#define REG_HMEBOX_DBG_0_8723B	0x0088
#define REG_HMEBOX_DBG_1_8723B	0x008A
#define REG_HMEBOX_DBG_2_8723B	0x008C
#define REG_HMEBOX_DBG_3_8723B	0x008E
#define REG_HIMR0_8723B					0x00B0
#define REG_HISR0_8723B					0x00B4
#define REG_HIMR1_8723B					0x00B8
#define REG_HISR1_8723B					0x00BC
#define REG_PMC_DBG_CTRL2_8723B			0x00CC

/*  */
/*  */
/*	0x0100h ~ 0x01FFh	MACTOP General Configuration */
/*  */
/*  */
#define REG_C2HEVT_CMD_ID_8723B	0x01A0
#define REG_C2HEVT_CMD_LEN_8723B	0x01AE
#define REG_WOWLAN_WAKE_REASON 0x01C7
#define REG_WOWLAN_GTK_DBG1	0x630
#define REG_WOWLAN_GTK_DBG2	0x634

#define REG_HMEBOX_EXT0_8723B			0x01F0
#define REG_HMEBOX_EXT1_8723B			0x01F4
#define REG_HMEBOX_EXT2_8723B			0x01F8
#define REG_HMEBOX_EXT3_8723B			0x01FC

/*  */
/*  */
/*	0x0200h ~ 0x027Fh	TXDMA Configuration */
/*  */
/*  */

/*  */
/*  */
/*	0x0280h ~ 0x02FFh	RXDMA Configuration */
/*  */
/*  */
#define REG_RXDMA_CONTROL_8723B		0x0286 /*  Control the RX DMA. */
#define REG_RXDMA_MODE_CTRL_8723B		0x0290

/*  */
/*  */
/*	0x0300h ~ 0x03FFh	PCIe */
/*  */
/*  */
#define	REG_PCIE_CTRL_REG_8723B		0x0300
#define	REG_INT_MIG_8723B				0x0304	/*  Interrupt Migration */
#define	REG_BCNQ_DESA_8723B			0x0308	/*  TX Beacon Descriptor Address */
#define	REG_HQ_DESA_8723B				0x0310	/*  TX High Queue Descriptor Address */
#define	REG_MGQ_DESA_8723B			0x0318	/*  TX Manage Queue Descriptor Address */
#define	REG_VOQ_DESA_8723B			0x0320	/*  TX VO Queue Descriptor Address */
#define	REG_VIQ_DESA_8723B				0x0328	/*  TX VI Queue Descriptor Address */
#define	REG_BEQ_DESA_8723B			0x0330	/*  TX BE Queue Descriptor Address */
#define	REG_BKQ_DESA_8723B			0x0338	/*  TX BK Queue Descriptor Address */
#define	REG_RX_DESA_8723B				0x0340	/*  RX Queue	Descriptor Address */
#define	REG_DBI_WDATA_8723B			0x0348	/*  DBI Write Data */
#define	REG_DBI_RDATA_8723B			0x034C	/*  DBI Read Data */
#define	REG_DBI_ADDR_8723B				0x0350	/*  DBI Address */
#define	REG_DBI_FLAG_8723B				0x0352	/*  DBI Read/Write Flag */
#define	REG_MDIO_WDATA_8723B		0x0354	/*  MDIO for Write PCIE PHY */
#define	REG_MDIO_RDATA_8723B			0x0356	/*  MDIO for Reads PCIE PHY */
#define	REG_MDIO_CTL_8723B			0x0358	/*  MDIO for Control */
#define	REG_DBG_SEL_8723B				0x0360	/*  Debug Selection Register */
#define	REG_PCIE_HRPWM_8723B			0x0361	/* PCIe RPWM */
#define	REG_PCIE_HCPWM_8723B			0x0363	/* PCIe CPWM */
#define	REG_PCIE_MULTIFET_CTRL_8723B	0x036A	/* PCIE Multi-Fethc Control */

/*  */
/*  */
/*	0x0400h ~ 0x047Fh	Protocol Configuration */
/*  */
/*  */
#define REG_TXPKTBUF_BCNQ_BDNY_8723B	0x0424
#define REG_TXPKTBUF_MGQ_BDNY_8723B	0x0425
#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B	0x045D

Annotation

Implementation Notes