drivers/target/iscsi/cxgbit/cxgbit_ddp.c
Source file repositories/reference/linux-study-clean/drivers/target/iscsi/cxgbit/cxgbit_ddp.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/target/iscsi/cxgbit/cxgbit_ddp.c- Extension
.c- Size
- 8335 bytes
- Lines
- 331
- Domain
- Driver Families
- Bucket
- drivers/target
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
cxgbit.h
Detected Declarations
function Copyrightfunction cxgbit_ppod_init_idatafunction cxgbit_ppod_write_idatafunction cxgbit_ddp_set_mapfunction cxgbit_ddp_sgl_checkfunction cxgbit_ddp_reservefunction cxgbit_get_r2t_tttfunction cxgbit_unmap_cmdfunction cxgbit_ddp_init
Annotated Snippet
if (sg) {
ppod->addr[i] = cpu_to_be64(addr + offset);
offset += PAGE_SIZE;
if (offset == (len + sg->offset)) {
offset = 0;
sg = sg_next(sg);
if (sg) {
addr = sg_dma_address(sg);
len = sg_dma_len(sg);
}
}
} else {
ppod->addr[i] = 0ULL;
}
}
/*
* the fifth address needs to be repeated in the next ppod, so do
* not move sg
*/
if (sg_pp) {
*sg_pp = sg;
*sg_off = offset;
}
if (offset == len) {
offset = 0;
if (sg) {
sg = sg_next(sg);
if (sg)
addr = sg_dma_address(sg);
}
}
ppod->addr[i] = sg ? cpu_to_be64(addr + offset) : 0ULL;
}
static struct sk_buff *
cxgbit_ppod_init_idata(struct cxgbit_device *cdev, struct cxgbi_ppm *ppm,
unsigned int idx, unsigned int npods, unsigned int tid)
{
struct ulp_mem_io *req;
struct ulptx_idata *idata;
unsigned int pm_addr = (idx << PPOD_SIZE_SHIFT) + ppm->llimit;
unsigned int dlen = npods << PPOD_SIZE_SHIFT;
unsigned int wr_len = roundup(sizeof(struct ulp_mem_io) +
sizeof(struct ulptx_idata) + dlen, 16);
struct sk_buff *skb;
skb = alloc_skb(wr_len, GFP_KERNEL);
if (!skb)
return NULL;
req = __skb_put(skb, wr_len);
INIT_ULPTX_WR(req, wr_len, 0, tid);
req->wr.wr_hi = htonl(FW_WR_OP_V(FW_ULPTX_WR) |
FW_WR_ATOMIC_V(0));
req->cmd = htonl(ULPTX_CMD_V(ULP_TX_MEM_WRITE) |
ULP_MEMIO_ORDER_V(0) |
T5_ULP_MEMIO_IMM_V(1));
req->dlen = htonl(ULP_MEMIO_DATA_LEN_V(dlen >> 5));
req->lock_addr = htonl(ULP_MEMIO_ADDR_V(pm_addr >> 5));
req->len16 = htonl(DIV_ROUND_UP(wr_len - sizeof(req->wr), 16));
idata = (struct ulptx_idata *)(req + 1);
idata->cmd_more = htonl(ULPTX_CMD_V(ULP_TX_SC_IMM));
idata->len = htonl(dlen);
return skb;
}
static int
cxgbit_ppod_write_idata(struct cxgbi_ppm *ppm, struct cxgbit_sock *csk,
struct cxgbi_task_tag_info *ttinfo, unsigned int idx,
unsigned int npods, struct scatterlist **sg_pp,
unsigned int *sg_off)
{
struct cxgbit_device *cdev = csk->com.cdev;
struct sk_buff *skb;
struct ulp_mem_io *req;
struct ulptx_idata *idata;
struct cxgbi_pagepod *ppod;
unsigned int i;
skb = cxgbit_ppod_init_idata(cdev, ppm, idx, npods, csk->tid);
if (!skb)
return -ENOMEM;
req = (struct ulp_mem_io *)skb->data;
idata = (struct ulptx_idata *)(req + 1);
ppod = (struct cxgbi_pagepod *)(idata + 1);
Annotation
- Immediate include surface: `cxgbit.h`.
- Detected declarations: `function Copyright`, `function cxgbit_ppod_init_idata`, `function cxgbit_ppod_write_idata`, `function cxgbit_ddp_set_map`, `function cxgbit_ddp_sgl_check`, `function cxgbit_ddp_reserve`, `function cxgbit_get_r2t_ttt`, `function cxgbit_unmap_cmd`, `function cxgbit_ddp_init`.
- Atlas domain: Driver Families / drivers/target.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.