drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c

Source file repositories/reference/linux-study-clean/drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c

File Facts

System
Linux kernel
Corpus path
drivers/thermal/intel/int340x_thermal/processor_thermal_rapl.c
Extension
.c
Size
6907 bytes
Lines
196
Domain
Driver Families
Bucket
drivers/thermal
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * processor thermal device RFIM control
 * Copyright (c) 2020, Intel Corporation.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include "processor_thermal_device.h"

static struct rapl_if_priv rapl_mmio_priv;

/* bitmasks for RAPL MSRs, used by primitive access functions */
#define MMIO_ENERGY_STATUS_MASK			GENMASK(31, 0)

#define MMIO_POWER_LIMIT1_MASK			GENMASK(14, 0)
#define MMIO_POWER_LIMIT1_ENABLE		BIT(15)
#define MMIO_POWER_LIMIT1_CLAMP			BIT(16)

#define MMIO_POWER_LIMIT2_MASK			GENMASK_ULL(46, 32)
#define MMIO_POWER_LIMIT2_ENABLE		BIT_ULL(47)
#define MMIO_POWER_LIMIT2_CLAMP			BIT_ULL(48)

#define MMIO_POWER_LOW_LOCK			BIT(31)
#define MMIO_POWER_HIGH_LOCK			BIT_ULL(63)

#define MMIO_POWER_LIMIT4_MASK			GENMASK(12, 0)

#define MMIO_TIME_WINDOW1_MASK			GENMASK_ULL(23, 17)
#define MMIO_TIME_WINDOW2_MASK			GENMASK_ULL(55, 49)

#define MMIO_POWER_INFO_MAX_MASK		GENMASK_ULL(46, 32)
#define MMIO_POWER_INFO_MIN_MASK		GENMASK_ULL(30, 16)
#define MMIO_POWER_INFO_MAX_TIME_WIN_MASK	GENMASK_ULL(53, 48)
#define MMIO_POWER_INFO_THERMAL_SPEC_MASK	GENMASK(14, 0)

#define MMIO_PERF_STATUS_THROTTLE_TIME_MASK	GENMASK(31, 0)
#define MMIO_PP_POLICY_MASK			GENMASK(4, 0)

/* RAPL primitives for MMIO I/F */
static struct rapl_primitive_info rpi_mmio[NR_RAPL_PRIMITIVES] = {
	/* name, mask, shift, msr index, unit divisor */
	[POWER_LIMIT1]		= PRIMITIVE_INFO_INIT(POWER_LIMIT1, MMIO_POWER_LIMIT1_MASK, 0,
						      RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
	[POWER_LIMIT2]		= PRIMITIVE_INFO_INIT(POWER_LIMIT2, MMIO_POWER_LIMIT2_MASK, 32,
						      RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
	[POWER_LIMIT4]		= PRIMITIVE_INFO_INIT(POWER_LIMIT4, MMIO_POWER_LIMIT4_MASK, 0,
						      RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0),
	[ENERGY_COUNTER]	= PRIMITIVE_INFO_INIT(ENERGY_COUNTER, MMIO_ENERGY_STATUS_MASK, 0,
						      RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0),
	[FW_LOCK]		= PRIMITIVE_INFO_INIT(FW_LOCK, MMIO_POWER_LOW_LOCK, 31,
						      RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
	[FW_HIGH_LOCK]		= PRIMITIVE_INFO_INIT(FW_LOCK, MMIO_POWER_HIGH_LOCK, 63,
						      RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
	[PL1_ENABLE]		= PRIMITIVE_INFO_INIT(PL1_ENABLE, MMIO_POWER_LIMIT1_ENABLE, 15,
						      RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
	[PL1_CLAMP]		= PRIMITIVE_INFO_INIT(PL1_CLAMP, MMIO_POWER_LIMIT1_CLAMP, 16,
						      RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
	[PL2_ENABLE]		= PRIMITIVE_INFO_INIT(PL2_ENABLE, MMIO_POWER_LIMIT2_ENABLE, 47,
						      RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
	[PL2_CLAMP]		= PRIMITIVE_INFO_INIT(PL2_CLAMP, MMIO_POWER_LIMIT2_CLAMP, 48,
						      RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
	[TIME_WINDOW1]		= PRIMITIVE_INFO_INIT(TIME_WINDOW1, MMIO_TIME_WINDOW1_MASK, 17,
						      RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
	[TIME_WINDOW2]		= PRIMITIVE_INFO_INIT(TIME_WINDOW2, MMIO_TIME_WINDOW2_MASK, 49,
						      RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
	[THERMAL_SPEC_POWER]	= PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER,
						      MMIO_POWER_INFO_THERMAL_SPEC_MASK, 0,
						      RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
	[MAX_POWER]		= PRIMITIVE_INFO_INIT(MAX_POWER, MMIO_POWER_INFO_MAX_MASK, 32,
						      RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
	[MIN_POWER]		= PRIMITIVE_INFO_INIT(MIN_POWER, MMIO_POWER_INFO_MIN_MASK, 16,
						      RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
	[MAX_TIME_WINDOW]	= PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW,
						      MMIO_POWER_INFO_MAX_TIME_WIN_MASK, 48,
						      RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0),
	[THROTTLED_TIME]	= PRIMITIVE_INFO_INIT(THROTTLED_TIME,
						      MMIO_PERF_STATUS_THROTTLE_TIME_MASK, 0,
						      RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0),
	[PRIORITY_LEVEL]	= PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, MMIO_PP_POLICY_MASK, 0,
						      RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0),
};

static const struct rapl_mmio_regs rapl_mmio_default = {
	.reg_unit = 0x5938,
	.regs[RAPL_DOMAIN_PACKAGE] = { 0x59a0, 0x593c, 0x58f0, 0, 0x5930, 0x59b0},
	.regs[RAPL_DOMAIN_DRAM] = { 0x58e0, 0x58e8, 0x58ec, 0, 0},
	.limits[RAPL_DOMAIN_PACKAGE] = BIT(POWER_LIMIT2) | BIT(POWER_LIMIT4),
	.limits[RAPL_DOMAIN_DRAM] = BIT(POWER_LIMIT2),

Annotation

Implementation Notes