drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c

Source file repositories/reference/linux-study-clean/drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c

File Facts

System
Linux kernel
Corpus path
drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c
Extension
.c
Size
15209 bytes
Lines
525
Domain
Driver Families
Bucket
drivers/thermal
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct mmio_reg {
	int read_only;
	u32 offset;
	int bits;
	u16 mask;
	u16 shift;
};

struct mapping_table {
	const char *attr_name;
	const u32 value;
	const char *mapped_str;
};

/* These will represent sysfs attribute names */
static const char * const fivr_strings[] = {
	"vco_ref_code_lo",
	"vco_ref_code_hi",
	"spread_spectrum_pct",
	"spread_spectrum_clk_enable",
	"rfi_vco_ref_code",
	"fivr_fffc_rev",
	NULL
};

static const struct mmio_reg tgl_fivr_mmio_regs[] = {
	{ 0, 0x5A18, 3, 0x7, 11}, /* vco_ref_code_lo */
	{ 0, 0x5A18, 8, 0xFF, 16}, /* vco_ref_code_hi */
	{ 0, 0x5A08, 8, 0xFF, 0}, /* spread_spectrum_pct */
	{ 0, 0x5A08, 1, 0x1, 8}, /* spread_spectrum_clk_enable */
	{ 1, 0x5A10, 12, 0xFFF, 0}, /* rfi_vco_ref_code */
	{ 1, 0x5A14, 2, 0x3, 1}, /* fivr_fffc_rev */
};

static const char * const dlvr_strings[] = {
	"dlvr_spread_spectrum_pct",
	"dlvr_control_mode",
	"dlvr_control_lock",
	"dlvr_rfim_enable",
	"dlvr_freq_select",
	"dlvr_hardware_rev",
	"dlvr_freq_mhz",
	"dlvr_pll_busy",
	NULL
};

static const struct mmio_reg dlvr_mmio_regs[] = {
	{ 0, 0x15A08, 5, 0x1F, 0}, /* dlvr_spread_spectrum_pct */
	{ 0, 0x15A08, 1, 0x1, 5}, /* dlvr_control_mode */
	{ 0, 0x15A08, 1, 0x1, 6}, /* dlvr_control_lock */
	{ 0, 0x15A08, 1, 0x1, 7}, /* dlvr_rfim_enable */
	{ 0, 0x15A08, 12, 0xFFF, 8}, /* dlvr_freq_select */
	{ 1, 0x15A10, 2, 0x3, 30}, /* dlvr_hardware_rev */
	{ 1, 0x15A10, 16, 0xFFFF, 0}, /* dlvr_freq_mhz */
	{ 1, 0x15A10, 1, 0x1, 16}, /* dlvr_pll_busy */
};

static const struct mmio_reg lnl_dlvr_mmio_regs[] = {
	{ 0, 0x5A08, 5, 0x1F, 0}, /* dlvr_spread_spectrum_pct */
	{ 0, 0x5A08, 1, 0x1, 5}, /* dlvr_control_mode */
	{ 0, 0x5A08, 1, 0x1, 6}, /* dlvr_control_lock */
	{ 0, 0x5A08, 1, 0x1, 7}, /* dlvr_rfim_enable */
	{ 0, 0x5A08, 2, 0x3, 8}, /* dlvr_freq_select */
	{ 1, 0x5A10, 2, 0x3, 30}, /* dlvr_hardware_rev */
	{ 1, 0x5A10, 2, 0x3, 0}, /* dlvr_freq_mhz */
	{ 1, 0x5A10, 1, 0x1, 23}, /* dlvr_pll_busy */
};

static const struct mapping_table lnl_dlvr_mapping[] = {
	{"dlvr_freq_select", 0, "2227.2"},
	{"dlvr_freq_select", 1, "2140"},
	{"dlvr_freq_mhz", 0, "2227.2"},
	{"dlvr_freq_mhz", 1, "2140"},
	{NULL, 0, NULL},
};

static const struct mmio_reg nvl_dlvr_mmio_regs[] = {
	{ 0, 0x19208, 5, 0x1F, 0}, /* dlvr_spread_spectrum_pct */
	{ 0, 0x19208, 1, 0x1, 5}, /* dlvr_control_mode */
	{ 0, 0x19208, 1, 0x1, 6}, /* dlvr_control_lock */
	{ 0, 0x19208, 1, 0x1, 7}, /* dlvr_rfim_enable */
	{ 0, 0x19208, 12, 0xFFF, 8}, /* dlvr_freq_select */
	{ 1, 0x19210, 2, 0x3, 30}, /* dlvr_hardware_rev */
	{ 1, 0x19210, 16, 0xFFFF, 0}, /* dlvr_freq_mhz */
	{ 1, 0x19210, 1, 0x1, 16}, /* dlvr_pll_busy */
};

static int match_mapping_table(const struct mapping_table *table, const char *attr_name,
			       bool match_int_value, const u32 value, const char *value_str,
			       char **result_str, u32 *result_int)

Annotation

Implementation Notes