drivers/thermal/tegra/tegra114-soctherm.c

Source file repositories/reference/linux-study-clean/drivers/thermal/tegra/tegra114-soctherm.c

File Facts

System
Linux kernel
Corpus path
drivers/thermal/tegra/tegra114-soctherm.c
Extension
.c
Size
6791 bytes
Lines
210
Domain
Driver Families
Bucket
drivers/thermal
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
 * Copyright (c) 2024, Svyatoslav Ryhel <clamor95@gmail.com>
 */

#include <linux/module.h>
#include <linux/platform_device.h>

#include <dt-bindings/thermal/tegra114-soctherm.h>

#include "soctherm.h"

#define TEGRA114_THERMTRIP_ANY_EN_MASK		(0x1 << 28)
#define TEGRA114_THERMTRIP_MEM_EN_MASK		(0x1 << 27)
#define TEGRA114_THERMTRIP_GPU_EN_MASK		(0x1 << 26)
#define TEGRA114_THERMTRIP_CPU_EN_MASK		(0x1 << 25)
#define TEGRA114_THERMTRIP_TSENSE_EN_MASK	(0x1 << 24)
#define TEGRA114_THERMTRIP_GPUMEM_THRESH_MASK	(0xff << 16)
#define TEGRA114_THERMTRIP_CPU_THRESH_MASK	(0xff << 8)
#define TEGRA114_THERMTRIP_TSENSE_THRESH_MASK	0xff

#define TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK	(0xff << 17)
#define TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK	(0xff << 9)

#define TEGRA114_THRESH_GRAIN			1000
#define TEGRA114_BPTT				8

static const struct tegra_tsensor_configuration tegra114_tsensor_config = {
	.tall = 16300,
	.tiddq_en = 1,
	.ten_count = 1,
	.tsample = 163,
	.tsample_ate = 655,
};

static const struct tegra_tsensor_group tegra114_tsensor_group_cpu = {
	.id = TEGRA114_SOCTHERM_SENSOR_CPU,
	.name = "cpu",
	.sensor_temp_offset = SENSOR_TEMP1,
	.sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK,
	.pdiv = 10,
	.pdiv_ate = 10,
	.pdiv_mask = SENSOR_PDIV_CPU_MASK,
	.pllx_hotspot_diff = 6,
	.pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK,
	.thermtrip_any_en_mask = TEGRA114_THERMTRIP_ANY_EN_MASK,
	.thermtrip_enable_mask = TEGRA114_THERMTRIP_CPU_EN_MASK,
	.thermtrip_threshold_mask = TEGRA114_THERMTRIP_CPU_THRESH_MASK,
	.thermctl_isr_mask = THERM_IRQ_CPU_MASK,
	.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_CPU,
	.thermctl_lvl0_up_thresh_mask = TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK,
	.thermctl_lvl0_dn_thresh_mask = TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK,
};

static const struct tegra_tsensor_group tegra114_tsensor_group_gpu = {
	.id = TEGRA114_SOCTHERM_SENSOR_GPU,
	.name = "gpu",
	.sensor_temp_offset = SENSOR_TEMP1,
	.sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK,
	.pdiv = 10,
	.pdiv_ate = 10,
	.pdiv_mask = SENSOR_PDIV_GPU_MASK,
	.pllx_hotspot_diff = 6,
	.pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK,
	.thermtrip_any_en_mask = TEGRA114_THERMTRIP_ANY_EN_MASK,
	.thermtrip_enable_mask = TEGRA114_THERMTRIP_GPU_EN_MASK,
	.thermtrip_threshold_mask = TEGRA114_THERMTRIP_GPUMEM_THRESH_MASK,
	.thermctl_isr_mask = THERM_IRQ_GPU_MASK,
	.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_GPU,
	.thermctl_lvl0_up_thresh_mask = TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK,
	.thermctl_lvl0_dn_thresh_mask = TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK,
};

static const struct tegra_tsensor_group tegra114_tsensor_group_pll = {
	.id = TEGRA114_SOCTHERM_SENSOR_PLLX,
	.name = "pll",
	.sensor_temp_offset = SENSOR_TEMP2,
	.sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK,
	.pdiv = 10,
	.pdiv_ate = 10,
	.pdiv_mask = SENSOR_PDIV_PLLX_MASK,
	.thermtrip_any_en_mask = TEGRA114_THERMTRIP_ANY_EN_MASK,
	.thermtrip_enable_mask = TEGRA114_THERMTRIP_TSENSE_EN_MASK,
	.thermtrip_threshold_mask = TEGRA114_THERMTRIP_TSENSE_THRESH_MASK,
	.thermctl_isr_mask = THERM_IRQ_TSENSE_MASK,
	.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_TSENSE,
	.thermctl_lvl0_up_thresh_mask = TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK,
	.thermctl_lvl0_dn_thresh_mask = TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK,
};

Annotation

Implementation Notes