drivers/thunderbolt/cap.c
Source file repositories/reference/linux-study-clean/drivers/thunderbolt/cap.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/thunderbolt/cap.c- Extension
.c- Size
- 5845 bytes
- Lines
- 257
- Domain
- Driver Families
- Bucket
- drivers/thunderbolt
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/slab.hlinux/errno.htb.h
Detected Declarations
function Copyrightfunction tb_port_dummy_readfunction tb_port_next_capfunction __tb_port_find_capfunction tb_port_find_capfunction tb_switch_next_capfunction tb_switch_find_capfunction tb_switch_find_vse_cap
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/*
* Thunderbolt driver - capabilities lookup
*
* Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
* Copyright (C) 2018, Intel Corporation
*/
#include <linux/slab.h>
#include <linux/errno.h>
#include "tb.h"
#define CAP_OFFSET_MAX 0xff
#define VSE_CAP_OFFSET_MAX 0xffff
#define TMU_ACCESS_EN BIT(20)
static int tb_port_enable_tmu(struct tb_port *port, bool enable)
{
struct tb_switch *sw = port->sw;
u32 value, offset;
int ret;
/*
* Legacy devices need to have TMU access enabled before port
* space can be fully accessed.
*/
if (tb_switch_is_light_ridge(sw))
offset = 0x26;
else if (tb_switch_is_eagle_ridge(sw))
offset = 0x2a;
else
return 0;
ret = tb_sw_read(sw, &value, TB_CFG_SWITCH, offset, 1);
if (ret)
return ret;
if (enable)
value |= TMU_ACCESS_EN;
else
value &= ~TMU_ACCESS_EN;
return tb_sw_write(sw, &value, TB_CFG_SWITCH, offset, 1);
}
static void tb_port_dummy_read(struct tb_port *port)
{
/*
* When reading from next capability pointer location in port
* config space the read data is not cleared on LR. To avoid
* reading stale data on next read perform one dummy read after
* port capabilities are walked.
*/
if (tb_switch_is_light_ridge(port->sw)) {
u32 dummy;
tb_port_read(port, &dummy, TB_CFG_PORT, 0, 1);
}
}
/**
* tb_port_next_cap() - Return next capability in the linked list
* @port: Port to find the capability for
* @offset: Previous capability offset (%0 for start)
*
* Finds dword offset of the next capability in port config space
* capability list. When passed %0 in @offset parameter, first entry
* will be returned, if it exists.
*
* Return:
* * Double word offset of the first or next capability - On success.
* * %0 - If no next capability is found.
* * Negative errno - Another error occurred.
*/
int tb_port_next_cap(struct tb_port *port, unsigned int offset)
{
struct tb_cap_any header;
int ret;
if (!offset)
return port->config.first_cap_offset;
ret = tb_port_read(port, &header, TB_CFG_PORT, offset, 1);
if (ret)
return ret;
return header.basic.next;
}
Annotation
- Immediate include surface: `linux/slab.h`, `linux/errno.h`, `tb.h`.
- Detected declarations: `function Copyright`, `function tb_port_dummy_read`, `function tb_port_next_cap`, `function __tb_port_find_cap`, `function tb_port_find_cap`, `function tb_switch_next_cap`, `function tb_switch_find_cap`, `function tb_switch_find_vse_cap`.
- Atlas domain: Driver Families / drivers/thunderbolt.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.