drivers/tty/ipwireless/hardware.c

Source file repositories/reference/linux-study-clean/drivers/tty/ipwireless/hardware.c

File Facts

System
Linux kernel
Corpus path
drivers/tty/ipwireless/hardware.c
Extension
.c
Size
46594 bytes
Lines
1771
Domain
Driver Families
Bucket
drivers/tty
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct nl_first_packet_header {
	unsigned char protocol:3;
	unsigned char address:3;
	unsigned char packet_rank:2;
	unsigned char length_lsb;
	unsigned char length_msb;
};

struct nl_packet_header {
	unsigned char protocol:3;
	unsigned char address:3;
	unsigned char packet_rank:2;
};

/* Value of 'packet_rank' above */
#define NL_INTERMEDIATE_PACKET    0x0
#define NL_LAST_PACKET            0x1
#define NL_FIRST_PACKET           0x2

union nl_packet {
	/* Network packet header of the first packet (a special case) */
	struct nl_first_packet_header hdr_first;
	/* Network packet header of the following packets (if any) */
	struct nl_packet_header hdr;
	/* Complete network packet (header + data) */
	unsigned char rawpkt[LL_MTU_MAX];
} __attribute__ ((__packed__));

#define HW_VERSION_UNKNOWN -1
#define HW_VERSION_1 1
#define HW_VERSION_2 2

/* IPW I/O ports */
#define IOIER 0x00		/* Interrupt Enable Register */
#define IOIR  0x02		/* Interrupt Source/ACK register */
#define IODCR 0x04		/* Data Control Register */
#define IODRR 0x06		/* Data Read Register */
#define IODWR 0x08		/* Data Write Register */
#define IOESR 0x0A		/* Embedded Driver Status Register */
#define IORXR 0x0C		/* Rx Fifo Register (Host to Embedded) */
#define IOTXR 0x0E		/* Tx Fifo Register (Embedded to Host) */

/* I/O ports and bit definitions for version 1 of the hardware */

/* IER bits*/
#define IER_RXENABLED   0x1
#define IER_TXENABLED   0x2

/* ISR bits */
#define IR_RXINTR       0x1
#define IR_TXINTR       0x2

/* DCR bits */
#define DCR_RXDONE      0x1
#define DCR_TXDONE      0x2
#define DCR_RXRESET     0x4
#define DCR_TXRESET     0x8

/* I/O ports and bit definitions for version 2 of the hardware */

struct MEMCCR {
	unsigned short reg_config_option;	/* PCCOR: Configuration Option Register */
	unsigned short reg_config_and_status;	/* PCCSR: Configuration and Status Register */
	unsigned short reg_pin_replacement;	/* PCPRR: Pin Replacemant Register */
	unsigned short reg_socket_and_copy;	/* PCSCR: Socket and Copy Register */
	unsigned short reg_ext_status;		/* PCESR: Extendend Status Register */
	unsigned short reg_io_base;		/* PCIOB: I/O Base Register */
};

struct MEMINFREG {
	unsigned short memreg_tx_old;	/* TX Register (R/W) */
	unsigned short pad1;
	unsigned short memreg_rx_done;	/* RXDone Register (R/W) */
	unsigned short pad2;
	unsigned short memreg_rx;	/* RX Register (R/W) */
	unsigned short pad3;
	unsigned short memreg_pc_interrupt_ack;	/* PC intr Ack Register (W) */
	unsigned short pad4;
	unsigned long memreg_card_present;/* Mask for Host to check (R) for
					   * CARD_PRESENT_VALUE */
	unsigned short memreg_tx_new;	/* TX2 (new) Register (R/W) */
};

#define CARD_PRESENT_VALUE (0xBEEFCAFEUL)

#define MEMTX_TX                       0x0001
#define MEMRX_RX                       0x0001
#define MEMRX_RX_DONE                  0x0001
#define MEMRX_PCINTACKK                0x0001

Annotation

Implementation Notes