drivers/tty/serial/zs.h

Source file repositories/reference/linux-study-clean/drivers/tty/serial/zs.h

File Facts

System
Linux kernel
Corpus path
drivers/tty/serial/zs.h
Extension
.h
Size
9692 bytes
Lines
285
Domain
Driver Families
Bucket
drivers/tty
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct zs_port {
	struct zs_scc	*scc;			/* Containing SCC.  */
	struct uart_port port;			/* Underlying UART.  */

	int		clk_mode;		/* May be 1, 16, 32, or 64.  */

	unsigned int	tty_break;		/* Set on BREAK condition.  */
	int		tx_stopped;		/* Output is suspended.  */

	unsigned int	mctrl;			/* State of modem lines.  */
	u8		brk;			/* BREAK state from RR0.  */

	u8		regs[ZS_NUM_REGS];	/* Channel write registers.  */
};

/*
 * Per-SCC state for locking and the interrupt handler.
 */
struct zs_scc {
	struct zs_port	zport[2];
	spinlock_t	zlock;
	atomic_t	irq_guard;
};

#endif /* __KERNEL__ */

/*
 * Conversion routines to/from brg time constants from/to bits per second.
 */
#define ZS_BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
#define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)

/*
 * The Zilog register set.
 */

/* Write Register 0 (Command) */
#define R0		0	/* Register selects */
#define R1		1
#define R2		2
#define R3		3
#define R4		4
#define R5		5
#define R6		6
#define R7		7
#define R8		8
#define R9		9
#define R10		10
#define R11		11
#define R12		12
#define R13		13
#define R14		14
#define R15		15

#define NULLCODE	0	/* Null Code */
#define POINT_HIGH	0x8	/* Select upper half of registers */
#define RES_EXT_INT	0x10	/* Reset Ext. Status Interrupts */
#define SEND_ABORT	0x18	/* HDLC Abort */
#define RES_RxINT_FC	0x20	/* Reset RxINT on First Character */
#define RES_Tx_P	0x28	/* Reset TxINT Pending */
#define ERR_RES		0x30	/* Error Reset */
#define RES_H_IUS	0x38	/* Reset highest IUS */

#define RES_Rx_CRC	0x40	/* Reset Rx CRC Checker */
#define RES_Tx_CRC	0x80	/* Reset Tx CRC Checker */
#define RES_EOM_L	0xC0	/* Reset EOM latch */

/* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
#define EXT_INT_ENAB	0x1	/* Ext Int Enable */
#define TxINT_ENAB	0x2	/* Tx Int Enable */
#define PAR_SPEC	0x4	/* Parity is special condition */

#define RxINT_DISAB	0	/* Rx Int Disable */
#define RxINT_FCERR	0x8	/* Rx Int on First Character Only or Error */
#define RxINT_ALL	0x10	/* Int on all Rx Characters or error */
#define RxINT_ERR	0x18	/* Int on error only */
#define RxINT_MASK	0x18

#define WT_RDY_RT	0x20	/* Wait/Ready on R/T */
#define WT_FN_RDYFN	0x40	/* Wait/FN/Ready FN */
#define WT_RDY_ENAB	0x80	/* Wait/Ready Enable */

/* Write Register 2 (Interrupt Vector) */

/* Write Register 3 (Receive Parameters and Control) */
#define RxENABLE	0x1	/* Rx Enable */
#define SYNC_L_INH	0x2	/* Sync Character Load Inhibit */
#define ADD_SM		0x4	/* Address Search Mode (SDLC) */
#define RxCRC_ENAB	0x8	/* Rx CRC Enable */
#define ENT_HM		0x10	/* Enter Hunt Mode */

Annotation

Implementation Notes