drivers/ufs/host/ufs-exynos.h

Source file repositories/reference/linux-study-clean/drivers/ufs/host/ufs-exynos.h

File Facts

System
Linux kernel
Corpus path
drivers/ufs/host/ufs-exynos.h
Extension
.h
Size
8211 bytes
Lines
295
Domain
Driver Families
Bucket
drivers/ufs
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct exynos_ufs_uic_attr {
	/* TX Attributes */
	unsigned int tx_trailingclks;
	unsigned int tx_dif_p_nsec;
	unsigned int tx_dif_n_nsec;
	unsigned int tx_high_z_cnt_nsec;
	unsigned int tx_base_unit_nsec;
	unsigned int tx_gran_unit_nsec;
	unsigned int tx_sleep_cnt;
	unsigned int tx_min_activatetime;
	/* RX Attributes */
	unsigned int rx_filler_enable;
	unsigned int rx_dif_p_nsec;
	unsigned int rx_hibern8_wait_nsec;
	unsigned int rx_base_unit_nsec;
	unsigned int rx_gran_unit_nsec;
	unsigned int rx_sleep_cnt;
	unsigned int rx_stall_cnt;
	unsigned int rx_hs_g1_sync_len_cap;
	unsigned int rx_hs_g2_sync_len_cap;
	unsigned int rx_hs_g3_sync_len_cap;
	unsigned int rx_hs_g1_prep_sync_len_cap;
	unsigned int rx_hs_g2_prep_sync_len_cap;
	unsigned int rx_hs_g3_prep_sync_len_cap;
	/* Common Attributes */
	unsigned int cmn_pwm_clk_ctrl;
	/* Internal Attributes */
	unsigned int pa_dbg_clk_period_off;
	unsigned int pa_dbg_opt_suite1_val;
	unsigned int pa_dbg_opt_suite1_off;
	unsigned int pa_dbg_opt_suite2_val;
	unsigned int pa_dbg_opt_suite2_off;
	/* Changeable Attributes */
	unsigned int rx_adv_fine_gran_sup_en;
	unsigned int rx_adv_fine_gran_step;
	unsigned int rx_min_actv_time_cap;
	unsigned int rx_hibern8_time_cap;
	unsigned int rx_adv_min_actv_time_cap;
	unsigned int rx_adv_hibern8_time_cap;
	unsigned int pa_granularity;
	unsigned int pa_tactivate;
	unsigned int pa_hibern8time;
};

struct exynos_ufs_drv_data {
	const struct ufs_hba_variant_ops *vops;
	struct exynos_ufs_uic_attr *uic_attr;
	unsigned int quirks;
	unsigned int opts;
	u32 iocc_mask;
	/* SoC's specific operations */
	int (*drv_init)(struct exynos_ufs *ufs);
	int (*pre_link)(struct exynos_ufs *ufs);
	int (*post_link)(struct exynos_ufs *ufs);
	int (*pre_pwr_change)(struct exynos_ufs *ufs,
				struct ufs_pa_layer_attr *pwr);
	int (*post_pwr_change)(struct exynos_ufs *ufs,
			       const struct ufs_pa_layer_attr *pwr);
	int (*pre_hce_enable)(struct exynos_ufs *ufs);
	int (*post_hce_enable)(struct exynos_ufs *ufs);
	int (*suspend)(struct exynos_ufs *ufs);
};

struct ufs_phy_time_cfg {
	u32 tx_linereset_p;
	u32 tx_linereset_n;
	u32 tx_high_z_cnt;
	u32 tx_base_n_val;
	u32 tx_gran_n_val;
	u32 tx_sleep_cnt;
	u32 rx_linereset;
	u32 rx_hibern8_wait;
	u32 rx_base_n_val;
	u32 rx_gran_n_val;
	u32 rx_sleep_cnt;
	u32 rx_stall_cnt;
};

struct exynos_ufs {
	struct ufs_hba *hba;
	struct phy *phy;
	void __iomem *reg_hci;
	void __iomem *reg_unipro;
	void __iomem *reg_ufsp;
	struct clk *clk_hci_core;
	struct clk *clk_unipro_main;
	struct clk *clk_apb;
	u32 pclk_rate;
	u32 pclk_div;
	u32 pclk_avail_min;

Annotation

Implementation Notes