drivers/ufs/host/ufs-qcom.h

Source file repositories/reference/linux-study-clean/drivers/ufs/host/ufs-qcom.h

File Facts

System
Linux kernel
Corpus path
drivers/ufs/host/ufs-qcom.h
Extension
.h
Size
11744 bytes
Lines
389
Domain
Driver Families
Bucket
drivers/ufs
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ufs_eom_coord {
	int t_step;
	int v_step;
	u8 eye_mask;
};

static const struct ufs_eom_coord sw_rx_fom_eom_coords_g6[SW_RX_FOM_EOM_COORDS] = {
	[0] = { -2, -15, UFS_EOM_EYE_MASK_M },
	[1] = { 0, -15, UFS_EOM_EYE_MASK_M },
	[2] = { 2, -15, UFS_EOM_EYE_MASK_M },
	[3] = { -4, -10, UFS_EOM_EYE_MASK_M },
	[4] = { -2, -10, UFS_EOM_EYE_MASK_M },
	[5] = { 0, -10, UFS_EOM_EYE_MASK_M },
	[6] = { 2, -10, UFS_EOM_EYE_MASK_M },
	[7] = { 4, -10, UFS_EOM_EYE_MASK_M },
	[8] = { -6, 0, UFS_EOM_EYE_MASK_M },
	[9] = { -4, 0, UFS_EOM_EYE_MASK_M },
	[10] = { -2, 0, UFS_EOM_EYE_MASK_M },
	[11] = { 0, 0, UFS_EOM_EYE_MASK_M },
	[12] = { 2, 0, UFS_EOM_EYE_MASK_M },
	[13] = { 4, 0, UFS_EOM_EYE_MASK_M },
	[14] = { 6, 0, UFS_EOM_EYE_MASK_M },
	[15] = { -4, 10, UFS_EOM_EYE_MASK_M },
	[16] = { -2, 10, UFS_EOM_EYE_MASK_M },
	[17] = { 0, 10, UFS_EOM_EYE_MASK_M },
	[18] = { 2, 10, UFS_EOM_EYE_MASK_M },
	[19] = { 4, 10, UFS_EOM_EYE_MASK_M },
	[20] = { -2, 15, UFS_EOM_EYE_MASK_M },
	[21] = { 0, 15, UFS_EOM_EYE_MASK_M },
	[22] = { 2, 15, UFS_EOM_EYE_MASK_M },
};

/* Qualcomm MCQ Configuration */
#define UFS_QCOM_MCQCAP_QCFGPTR     224  /* 0xE0 in hex */
#define UFS_QCOM_MCQ_CONFIG_OFFSET  (UFS_QCOM_MCQCAP_QCFGPTR * 0x200)  /* 0x1C000 */

/* Doorbell offsets within MCQ region (relative to MCQ_CONFIG_BASE) */
#define UFS_QCOM_MCQ_SQD_OFFSET     0x5000
#define UFS_QCOM_MCQ_CQD_OFFSET     0x5080
#define UFS_QCOM_MCQ_SQIS_OFFSET    0x5040
#define UFS_QCOM_MCQ_CQIS_OFFSET    0x50C0
#define UFS_QCOM_MCQ_STRIDE         0x100

/* Calculated doorbell address offsets (relative to mmio_base) */
#define UFS_QCOM_SQD_ADDR_OFFSET    (UFS_QCOM_MCQ_CONFIG_OFFSET + UFS_QCOM_MCQ_SQD_OFFSET)
#define UFS_QCOM_CQD_ADDR_OFFSET    (UFS_QCOM_MCQ_CONFIG_OFFSET + UFS_QCOM_MCQ_CQD_OFFSET)
#define UFS_QCOM_SQIS_ADDR_OFFSET   (UFS_QCOM_MCQ_CONFIG_OFFSET + UFS_QCOM_MCQ_SQIS_OFFSET)
#define UFS_QCOM_CQIS_ADDR_OFFSET   (UFS_QCOM_MCQ_CONFIG_OFFSET + UFS_QCOM_MCQ_CQIS_OFFSET)
#define REG_UFS_MCQ_STRIDE          UFS_QCOM_MCQ_STRIDE

/* MCQ Vendor specific address offsets (relative to MCQ_CONFIG_BASE) */
#define UFS_MEM_VS_BASE 0x4000
#define UFS_MEM_CQIS_VS 0x4008

/* QCOM UFS host controller vendor specific registers */
enum {
	REG_UFS_SYS1CLK_1US                 = 0xC0,
	REG_UFS_TX_SYMBOL_CLK_NS_US         = 0xC4,
	REG_UFS_LOCAL_PORT_ID_REG           = 0xC8,
	REG_UFS_PA_ERR_CODE                 = 0xCC,
	/* On older UFS revisions, this register is called "RETRY_TIMER_REG" */
	REG_UFS_PARAM0                      = 0xD0,
	/* On older UFS revisions, this register is called "REG_UFS_PA_LINK_STARTUP_TIMER" */
	REG_UFS_CFG0                        = 0xD8,
	REG_UFS_CFG1                        = 0xDC,
	REG_UFS_CFG2                        = 0xE0,
	REG_UFS_HW_VERSION                  = 0xE4,

	UFS_TEST_BUS				= 0xE8,
	UFS_TEST_BUS_CTRL_0			= 0xEC,
	UFS_TEST_BUS_CTRL_1			= 0xF0,
	UFS_TEST_BUS_CTRL_2			= 0xF4,
	UFS_UNIPRO_CFG				= 0xF8,

	/*
	 * QCOM UFS host controller vendor specific registers
	 * added in HW Version 3.0.0
	 */
	UFS_AH8_CFG				= 0xFC,

	UFS_RD_REG_MCQ				= 0xD00,
	UFS_MEM_ICE_CFG				= 0x2600,
	REG_UFS_MEM_ICE_CONFIG			= 0x260C,
	REG_UFS_MEM_ICE_NUM_CORE		= 0x2664,

	REG_UFS_CFG3				= 0x271C,

	REG_UFS_DEBUG_SPARE_CFG			= 0x284C,
};

Annotation

Implementation Notes