drivers/usb/dwc2/hcd.h

File Facts

System

Linux kernel

Corpus path

drivers/usb/dwc2/hcd.h

Extension

.h

Size

27055 bytes

Lines

788

Domain

Driver Families

Bucket

drivers/usb

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Touches IRQ or DMA behavior; this matters for the representative real-device path.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• struct dwc2_qh
• struct dwc2_host_chan
• struct dwc2_hcd_pipe_info
• struct dwc2_hcd_iso_packet_desc
• struct dwc2_qtd
• struct dwc2_hcd_urb
• struct dwc2_tt
• struct dwc2_hs_transfer_time
• struct dwc2_qh
• struct dwc2_qtd
• struct hc_xfer_info
• enum dwc2_control_phase
• enum dwc2_transaction_type
• function disable_hc_int
• function dwc2_read_hprt0
• function dwc2_hcd_get_ep_num
• function dwc2_hcd_get_pipe_type
• function dwc2_hcd_get_maxp
• function dwc2_hcd_get_maxp_mult
• function dwc2_hcd_get_dev_addr
• function dwc2_hcd_is_pipe_isoc
• function dwc2_hcd_is_pipe_int
• function dwc2_hcd_is_pipe_bulk
• function dwc2_hcd_is_pipe_control
• function dwc2_hcd_is_pipe_in
• function dwc2_hcd_is_pipe_out
• function dwc2_hcd_qtd_unlink_and_free
• function dbg_hc
• function dbg_qh
• function dbg_urb
• function dbg_perio
• function dbg_hc
• function dbg_qh
• function dbg_urb
• function dbg_perio
• function dwc2_frame_idx_num_gt
• function dwc2_frame_num_le
• function dwc2_frame_num_gt
• function dwc2_frame_num_inc
• function dwc2_frame_num_dec
• function dwc2_full_frame_num
• function dwc2_micro_frame_num
• function dwc2_read_core_intr
• function dwc2_hcd_urb_get_status
• function dwc2_hcd_urb_get_actual_length
• function dwc2_hcd_urb_get_error_count
• function dwc2_hcd_urb_set_iso_desc_params
• function dwc2_hcd_urb_get_iso_desc_status

Annotated Snippet

struct dwc2_host_chan {
	u8 hc_num;

	unsigned dev_addr:7;
	unsigned ep_num:4;
	unsigned ep_is_in:1;
	unsigned speed:4;
	unsigned ep_type:2;
	unsigned max_packet:11;
	unsigned data_pid_start:2;
#define DWC2_HC_PID_DATA0	TSIZ_SC_MC_PID_DATA0
#define DWC2_HC_PID_DATA2	TSIZ_SC_MC_PID_DATA2
#define DWC2_HC_PID_DATA1	TSIZ_SC_MC_PID_DATA1
#define DWC2_HC_PID_MDATA	TSIZ_SC_MC_PID_MDATA
#define DWC2_HC_PID_SETUP	TSIZ_SC_MC_PID_SETUP

	unsigned multi_count:2;

	u8 *xfer_buf;
	dma_addr_t xfer_dma;
	dma_addr_t align_buf;
	u32 xfer_len;
	u32 xfer_count;
	u16 start_pkt_count;
	u8 xfer_started;
	u8 do_ping;
	u8 error_state;
	u8 halt_on_queue;
	u8 halt_pending;
	u8 do_split;
	u8 complete_split;
	u8 hub_addr;
	u8 hub_port;
	u8 xact_pos;
#define DWC2_HCSPLT_XACTPOS_MID	HCSPLT_XACTPOS_MID
#define DWC2_HCSPLT_XACTPOS_END	HCSPLT_XACTPOS_END
#define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN
#define DWC2_HCSPLT_XACTPOS_ALL	HCSPLT_XACTPOS_ALL

	u8 requests;
	u8 schinfo;
	u16 ntd;
	enum dwc2_halt_status halt_status;
	u32 hcint;
	struct dwc2_qh *qh;
	struct list_head hc_list_entry;
	dma_addr_t desc_list_addr;
	u32 desc_list_sz;
	struct list_head split_order_list_entry;
};

struct dwc2_hcd_pipe_info {
	u8 dev_addr;
	u8 ep_num;
	u8 pipe_type;
	u8 pipe_dir;
	u16 maxp;
	u16 maxp_mult;
};

struct dwc2_hcd_iso_packet_desc {
	u32 offset;
	u32 length;
	u32 actual_length;
	u32 status;
};

struct dwc2_qtd;

struct dwc2_hcd_urb {
	void *priv;
	struct dwc2_qtd *qtd;
	void *buf;
	dma_addr_t dma;
	void *setup_packet;
	dma_addr_t setup_dma;
	u32 length;
	u32 actual_length;
	u32 status;
	u32 error_count;
	u32 packet_count;
	u32 flags;
	u16 interval;
	struct dwc2_hcd_pipe_info pipe_info;
	struct dwc2_hcd_iso_packet_desc iso_descs[];
};

/* Phases for control transfers */
enum dwc2_control_phase {
	DWC2_CONTROL_SETUP,

Annotation

• Detected declarations: `struct dwc2_qh`, `struct dwc2_host_chan`, `struct dwc2_hcd_pipe_info`, `struct dwc2_hcd_iso_packet_desc`, `struct dwc2_qtd`, `struct dwc2_hcd_urb`, `struct dwc2_tt`, `struct dwc2_hs_transfer_time`, `struct dwc2_qh`, `struct dwc2_qtd`.
• Atlas domain: Driver Families / drivers/usb.
• Implementation status: source implementation candidate.
• IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.