drivers/usb/dwc2/hw.h

Source file repositories/reference/linux-study-clean/drivers/usb/dwc2/hw.h

File Facts

System
Linux kernel
Corpus path
drivers/usb/dwc2/hw.h
Extension
.h
Size
30495 bytes
Lines
890
Domain
Driver Families
Bucket
drivers/usb
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dwc2_dma_desc {
	u32 status;
	u32 buf;
} __packed;

/* Host Mode DMA descriptor status quadlet */

#define HOST_DMA_A			BIT(31)
#define HOST_DMA_STS_MASK		(0x3 << 28)
#define HOST_DMA_STS_SHIFT		28
#define HOST_DMA_STS_PKTERR		BIT(28)
#define HOST_DMA_EOL			BIT(26)
#define HOST_DMA_IOC			BIT(25)
#define HOST_DMA_SUP			BIT(24)
#define HOST_DMA_ALT_QTD		BIT(23)
#define HOST_DMA_QTD_OFFSET_MASK	(0x3f << 17)
#define HOST_DMA_QTD_OFFSET_SHIFT	17
#define HOST_DMA_ISOC_NBYTES_MASK	(0xfff << 0)
#define HOST_DMA_ISOC_NBYTES_SHIFT	0
#define HOST_DMA_NBYTES_MASK		(0x1ffff << 0)
#define HOST_DMA_NBYTES_SHIFT		0
#define HOST_DMA_NBYTES_LIMIT		131071

/* Device Mode DMA descriptor status quadlet */

#define DEV_DMA_BUFF_STS_MASK		(0x3 << 30)
#define DEV_DMA_BUFF_STS_SHIFT		30
#define DEV_DMA_BUFF_STS_HREADY		0
#define DEV_DMA_BUFF_STS_DMABUSY	1
#define DEV_DMA_BUFF_STS_DMADONE	2
#define DEV_DMA_BUFF_STS_HBUSY		3
#define DEV_DMA_STS_MASK		(0x3 << 28)
#define DEV_DMA_STS_SHIFT		28
#define DEV_DMA_STS_SUCC		0
#define DEV_DMA_STS_BUFF_FLUSH		1
#define DEV_DMA_STS_BUFF_ERR		3
#define DEV_DMA_L			BIT(27)
#define DEV_DMA_SHORT			BIT(26)
#define DEV_DMA_IOC			BIT(25)
#define DEV_DMA_SR			BIT(24)
#define DEV_DMA_MTRF			BIT(23)
#define DEV_DMA_ISOC_PID_MASK		(0x3 << 23)
#define DEV_DMA_ISOC_PID_SHIFT		23
#define DEV_DMA_ISOC_PID_DATA0		0
#define DEV_DMA_ISOC_PID_DATA2		1
#define DEV_DMA_ISOC_PID_DATA1		2
#define DEV_DMA_ISOC_PID_MDATA		3
#define DEV_DMA_ISOC_FRNUM_MASK		(0x7ff << 12)
#define DEV_DMA_ISOC_FRNUM_SHIFT	12
#define DEV_DMA_ISOC_TX_NBYTES_MASK	(0xfff << 0)
#define DEV_DMA_ISOC_TX_NBYTES_LIMIT	0xfff
#define DEV_DMA_ISOC_RX_NBYTES_MASK	(0x7ff << 0)
#define DEV_DMA_ISOC_RX_NBYTES_LIMIT	0x7ff
#define DEV_DMA_ISOC_NBYTES_SHIFT	0
#define DEV_DMA_NBYTES_MASK		(0xffff << 0)
#define DEV_DMA_NBYTES_SHIFT		0
#define DEV_DMA_NBYTES_LIMIT		0xffff

#define MAX_DMA_DESC_NUM_GENERIC	64
#define MAX_DMA_DESC_NUM_HS_ISOC	256

#endif /* __DWC2_HW_H__ */

Annotation

Implementation Notes