drivers/usb/dwc3/core.h

Source file repositories/reference/linux-study-clean/drivers/usb/dwc3/core.h

File Facts

System
Linux kernel
Corpus path
drivers/usb/dwc3/core.h
Extension
.h
Size
57832 bytes
Lines
1748
Domain
Driver Families
Bucket
drivers/usb
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dwc3_event_buffer {
	void			*buf;
	void			*cache;
	unsigned int		length;
	unsigned int		lpos;
	unsigned int		count;
	unsigned int		flags;

#define DWC3_EVENT_PENDING	BIT(0)

	dma_addr_t		dma;

	struct dwc3		*dwc;
};

#define DWC3_EP_FLAG_STALLED	BIT(0)
#define DWC3_EP_FLAG_WEDGED	BIT(1)

#define DWC3_EP_DIRECTION_TX	true
#define DWC3_EP_DIRECTION_RX	false

#define DWC3_TRB_NUM		256

/**
 * struct dwc3_ep - device side endpoint representation
 * @endpoint: usb endpoint
 * @nostream_work: work for handling bulk NoStream
 * @cancelled_list: list of cancelled requests for this endpoint
 * @pending_list: list of pending requests for this endpoint
 * @started_list: list of started requests on this endpoint
 * @regs: pointer to first endpoint register
 * @trb_pool: array of transaction buffers
 * @trb_pool_dma: dma address of @trb_pool
 * @trb_enqueue: enqueue 'pointer' into TRB array
 * @trb_dequeue: dequeue 'pointer' into TRB array
 * @dwc: pointer to DWC controller
 * @saved_state: ep state saved during hibernation
 * @flags: endpoint flags (wedged, stalled, ...)
 * @number: endpoint number (1 - 15)
 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
 * @resource_index: Resource transfer index
 * @frame_number: set to the frame number we want this transfer to start (ISOC)
 * @interval: the interval on which the ISOC transfer is started
 * @name: a human readable name e.g. ep1out-bulk
 * @direction: true for TX, false for RX
 * @stream_capable: true when streams are enabled
 * @combo_num: the test combination BIT[15:14] of the frame number to test
 *		isochronous START TRANSFER command failure workaround
 * @start_cmd_status: the status of testing START TRANSFER command with
 *		combo_num = 'b00
 */
struct dwc3_ep {
	struct usb_ep		endpoint;
	struct delayed_work	nostream_work;
	struct list_head	cancelled_list;
	struct list_head	pending_list;
	struct list_head	started_list;

	struct dwc3_trb		*trb_pool;
	dma_addr_t		trb_pool_dma;
	struct dwc3		*dwc;

	u32			saved_state;
	unsigned int		flags;
#define DWC3_EP_ENABLED			BIT(0)
#define DWC3_EP_STALL			BIT(1)
#define DWC3_EP_WEDGE			BIT(2)
#define DWC3_EP_TRANSFER_STARTED	BIT(3)
#define DWC3_EP_END_TRANSFER_PENDING	BIT(4)
#define DWC3_EP_PENDING_REQUEST		BIT(5)
#define DWC3_EP_DELAY_START		BIT(6)
#define DWC3_EP_WAIT_TRANSFER_COMPLETE	BIT(7)
#define DWC3_EP_IGNORE_NEXT_NOSTREAM	BIT(8)
#define DWC3_EP_FORCE_RESTART_STREAM	BIT(9)
#define DWC3_EP_STREAM_PRIMED		BIT(10)
#define DWC3_EP_PENDING_CLEAR_STALL	BIT(11)
#define DWC3_EP_TXFIFO_RESIZED		BIT(12)
#define DWC3_EP_DELAY_STOP             BIT(13)
#define DWC3_EP_RESOURCE_ALLOCATED	BIT(14)

	/* This last one is specific to EP0 */
#define DWC3_EP0_DIR_IN			BIT(31)

	/*
	 * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will
	 * use a u8 type here. If anybody decides to increase number of TRBs to
	 * anything larger than 256 - I can't see why people would want to do
	 * this though - then this type needs to be changed.
	 *
	 * By using u8 types we ensure that our % operator when incrementing

Annotation

Implementation Notes