drivers/usb/gadget/udc/cdns2/cdns2-gadget.h

Source file repositories/reference/linux-study-clean/drivers/usb/gadget/udc/cdns2/cdns2-gadget.h

File Facts

System
Linux kernel
Corpus path
drivers/usb/gadget/udc/cdns2/cdns2-gadget.h
Extension
.h
Size
21797 bytes
Lines
717
Domain
Driver Families
Bucket
drivers/usb
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct cdns2_ep0_regs {
	__u8 rxbc;
	__u8 txbc;
	__u8 cs;
	__u8 reserved1[4];
	__u8 fifo;
	__le32 reserved2[94];
	__u8 setupdat[8];
	__u8 reserved4[88];
	__u8 maxpack;
} __packed __aligned(4);

/* EP0CS - bitmasks. */
/* Endpoint 0 stall bit for status stage. */
#define EP0CS_STALL	BIT(0)
/* HSNAK bit. */
#define EP0CS_HSNAK	BIT(1)
/* IN 0 endpoint busy bit. */
#define EP0CS_TXBSY_MSK	BIT(2)
/* OUT 0 endpoint busy bit. */
#define EP0CS_RXBSY_MSK	BIT(3)
/* Send STALL in the data stage phase. */
#define EP0CS_DSTALL	BIT(4)
/* SETUP buffer content was changed. */
#define EP0CS_CHGSET	BIT(7)

/* EP0FIFO - bitmasks. */
/* Direction. */
#define EP0_FIFO_IO_TX	BIT(4)
/* FIFO auto bit. */
#define EP0_FIFO_AUTO	BIT(5)
/* FIFO commit bit. */
#define EP0_FIFO_COMMIT	BIT(6)
/* FIFO access bit. */
#define EP0_FIFO_ACCES	BIT(7)

/**
 * struct cdns2_epx_base - base endpoint registers.
 * @rxbc: OUT endpoint byte count register.
 * @rxcon: OUT endpoint control register.
 * @rxcs: OUT endpoint control and status register.
 * @txbc: IN endpoint byte count register.
 * @txcon: IN endpoint control register.
 * @txcs: IN endpoint control and status register.
 */
struct cdns2_epx_base {
	__le16 rxbc;
	__u8 rxcon;
	__u8 rxcs;
	__le16 txbc;
	__u8 txcon;
	__u8 txcs;
} __packed __aligned(4);

/* rxcon/txcon - endpoint control register bitmasks. */
/* Endpoint buffering: 0 - single buffering ... 3 - quad buffering. */
#define EPX_CON_BUF		GENMASK(1, 0)
/* Endpoint type. */
#define EPX_CON_TYPE		GENMASK(3, 2)
/* Endpoint type: isochronous. */
#define EPX_CON_TYPE_ISOC	0x4
/* Endpoint type: bulk. */
#define EPX_CON_TYPE_BULK	0x8
/* Endpoint type: interrupt. */
#define EPX_CON_TYPE_INT	0xC
/* Number of packets per microframe. */
#define EPX_CON_ISOD		GENMASK(5, 4)
#define EPX_CON_ISOD_SHIFT	0x4
/* Endpoint stall bit. */
#define EPX_CON_STALL		BIT(6)
/* Endpoint enable bit.*/
#define EPX_CON_VAL		BIT(7)

/* rxcs/txcs - endpoint control and status bitmasks. */
/* Data sequence error for the ISO endpoint. */
#define EPX_CS_ERR(p)		((p) & BIT(0))

/**
 * struct cdns2_epx_regs - endpoint 1..15 related registers.
 * @reserved: reserved.
 * @ep: none control endpoints array.
 * @reserved2: reserved.
 * @endprst: endpoint reset register.
 * @reserved3: reserved.
 * @isoautoarm: ISO auto-arm register.
 * @reserved4: reserved.
 * @isodctrl: ISO control register.
 * @reserved5: reserved.
 * @isoautodump: ISO auto dump enable register.
 * @reserved6: reserved.

Annotation

Implementation Notes