drivers/usb/gadget/udc/gr_udc.h
Source file repositories/reference/linux-study-clean/drivers/usb/gadget/udc/gr_udc.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/usb/gadget/udc/gr_udc.h- Extension
.h- Size
- 5514 bytes
- Lines
- 221
- Domain
- Driver Families
- Bucket
- drivers/usb
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
struct gr_epregsstruct gr_regsstruct gr_dma_descstruct gr_epstruct gr_requeststruct gr_udcenum gr_ep0state
Annotated Snippet
struct gr_epregs {
u32 epctrl;
union {
struct { /* Slave mode*/
u32 slvctrl;
u32 slvdata;
};
struct { /* DMA mode*/
u32 dmactrl;
u32 dmaaddr;
};
};
u32 epstat;
};
struct gr_regs {
struct gr_epregs epo[GR_MAXEP]; /* 0x000 - 0x0fc */
struct gr_epregs epi[GR_MAXEP]; /* 0x100 - 0x1fc */
u32 control; /* 0x200 */
u32 status; /* 0x204 */
};
#define GR_EPCTRL_BUFSZ_SCALER 8
#define GR_EPCTRL_BUFSZ_MASK 0xffe00000
#define GR_EPCTRL_BUFSZ_POS 21
#define GR_EPCTRL_PI BIT(20)
#define GR_EPCTRL_CB BIT(19)
#define GR_EPCTRL_CS BIT(18)
#define GR_EPCTRL_MAXPL_MASK 0x0003ff80
#define GR_EPCTRL_MAXPL_POS 7
#define GR_EPCTRL_NT_MASK 0x00000060
#define GR_EPCTRL_NT_POS 5
#define GR_EPCTRL_TT_MASK 0x00000018
#define GR_EPCTRL_TT_POS 3
#define GR_EPCTRL_EH BIT(2)
#define GR_EPCTRL_ED BIT(1)
#define GR_EPCTRL_EV BIT(0)
#define GR_DMACTRL_AE BIT(10)
#define GR_DMACTRL_AD BIT(3)
#define GR_DMACTRL_AI BIT(2)
#define GR_DMACTRL_IE BIT(1)
#define GR_DMACTRL_DA BIT(0)
#define GR_EPSTAT_PT BIT(29)
#define GR_EPSTAT_PR BIT(29)
#define GR_EPSTAT_B1CNT_MASK 0x1fff0000
#define GR_EPSTAT_B1CNT_POS 16
#define GR_EPSTAT_B0CNT_MASK 0x0000fff8
#define GR_EPSTAT_B0CNT_POS 3
#define GR_EPSTAT_B1 BIT(2)
#define GR_EPSTAT_B0 BIT(1)
#define GR_EPSTAT_BS BIT(0)
#define GR_CONTROL_SI BIT(31)
#define GR_CONTROL_UI BIT(30)
#define GR_CONTROL_VI BIT(29)
#define GR_CONTROL_SP BIT(28)
#define GR_CONTROL_FI BIT(27)
#define GR_CONTROL_EP BIT(14)
#define GR_CONTROL_DH BIT(13)
#define GR_CONTROL_RW BIT(12)
#define GR_CONTROL_TS_MASK 0x00000e00
#define GR_CONTROL_TS_POS 9
#define GR_CONTROL_TM BIT(8)
#define GR_CONTROL_UA_MASK 0x000000fe
#define GR_CONTROL_UA_POS 1
#define GR_CONTROL_SU BIT(0)
#define GR_STATUS_NEPI_MASK 0xf0000000
#define GR_STATUS_NEPI_POS 28
#define GR_STATUS_NEPO_MASK 0x0f000000
#define GR_STATUS_NEPO_POS 24
#define GR_STATUS_DM BIT(23)
#define GR_STATUS_SU BIT(17)
#define GR_STATUS_UR BIT(16)
#define GR_STATUS_VB BIT(15)
#define GR_STATUS_SP BIT(14)
#define GR_STATUS_AF_MASK 0x00003800
#define GR_STATUS_AF_POS 11
#define GR_STATUS_FN_MASK 0x000007ff
#define GR_STATUS_FN_POS 0
#define MAX_CTRL_PL_SIZE 64 /* As per USB standard for full and high speed */
/*-------------------------------------------------------------------------*/
/* Driver data structures and utilities */
Annotation
- Detected declarations: `struct gr_epregs`, `struct gr_regs`, `struct gr_dma_desc`, `struct gr_ep`, `struct gr_request`, `struct gr_udc`, `enum gr_ep0state`.
- Atlas domain: Driver Families / drivers/usb.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.