drivers/usb/mtu3/mtu3_hw_regs.h

Source file repositories/reference/linux-study-clean/drivers/usb/mtu3/mtu3_hw_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/usb/mtu3/mtu3_hw_regs.h
Extension
.h
Size
17640 bytes
Lines
544
Domain
Driver Families
Bucket
drivers/usb
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _SSUSB_HW_REGS_H_
#define _SSUSB_HW_REGS_H_

/* segment offset of MAC register */
#define SSUSB_DEV_BASE		0x0000
#define SSUSB_EPCTL_CSR_BASE	0x0800
#define SSUSB_USB3_MAC_CSR_BASE	0x1400
#define SSUSB_USB3_SYS_CSR_BASE	0x1400
#define SSUSB_USB2_CSR_BASE	0x2400

/* IPPC register in Infra */
#define SSUSB_SIFSLV_IPPC_BASE	0x0000

/* --------------- SSUSB_DEV REGISTER DEFINITION --------------- */

#define U3D_LV1ISR		(SSUSB_DEV_BASE + 0x0000)
#define U3D_LV1IER		(SSUSB_DEV_BASE + 0x0004)
#define U3D_LV1IESR		(SSUSB_DEV_BASE + 0x0008)
#define U3D_LV1IECR		(SSUSB_DEV_BASE + 0x000C)

#define U3D_EPISR		(SSUSB_DEV_BASE + 0x0080)
#define U3D_EPIER		(SSUSB_DEV_BASE + 0x0084)
#define U3D_EPIESR		(SSUSB_DEV_BASE + 0x0088)
#define U3D_EPIECR		(SSUSB_DEV_BASE + 0x008C)

#define U3D_EP0CSR		(SSUSB_DEV_BASE + 0x0100)
#define U3D_RXCOUNT0		(SSUSB_DEV_BASE + 0x0108)
#define U3D_RESERVED		(SSUSB_DEV_BASE + 0x010C)
#define U3D_TX1CSR0		(SSUSB_DEV_BASE + 0x0110)
#define U3D_TX1CSR1		(SSUSB_DEV_BASE + 0x0114)
#define U3D_TX1CSR2		(SSUSB_DEV_BASE + 0x0118)

#define U3D_RX1CSR0		(SSUSB_DEV_BASE + 0x0210)
#define U3D_RX1CSR1		(SSUSB_DEV_BASE + 0x0214)
#define U3D_RX1CSR2		(SSUSB_DEV_BASE + 0x0218)

#define U3D_FIFO0		(SSUSB_DEV_BASE + 0x0300)

#define U3D_QCR0		(SSUSB_DEV_BASE + 0x0400)
#define U3D_QCR1		(SSUSB_DEV_BASE + 0x0404)
#define U3D_QCR2		(SSUSB_DEV_BASE + 0x0408)
#define U3D_QCR3		(SSUSB_DEV_BASE + 0x040C)
#define U3D_QFCR		(SSUSB_DEV_BASE + 0x0428)
#define U3D_TXQHIAR1		(SSUSB_DEV_BASE + 0x0484)
#define U3D_RXQHIAR1		(SSUSB_DEV_BASE + 0x04C4)

#define U3D_TXQCSR1		(SSUSB_DEV_BASE + 0x0510)
#define U3D_TXQSAR1		(SSUSB_DEV_BASE + 0x0514)
#define U3D_TXQCPR1		(SSUSB_DEV_BASE + 0x0518)

#define U3D_RXQCSR1		(SSUSB_DEV_BASE + 0x0610)
#define U3D_RXQSAR1		(SSUSB_DEV_BASE + 0x0614)
#define U3D_RXQCPR1		(SSUSB_DEV_BASE + 0x0618)
#define U3D_RXQLDPR1		(SSUSB_DEV_BASE + 0x061C)

#define U3D_QISAR0		(SSUSB_DEV_BASE + 0x0700)
#define U3D_QIER0		(SSUSB_DEV_BASE + 0x0704)
#define U3D_QIESR0		(SSUSB_DEV_BASE + 0x0708)
#define U3D_QIECR0		(SSUSB_DEV_BASE + 0x070C)
#define U3D_QISAR1		(SSUSB_DEV_BASE + 0x0710)
#define U3D_QIER1		(SSUSB_DEV_BASE + 0x0714)
#define U3D_QIESR1		(SSUSB_DEV_BASE + 0x0718)
#define U3D_QIECR1		(SSUSB_DEV_BASE + 0x071C)

#define U3D_TQERRIR0		(SSUSB_DEV_BASE + 0x0780)
#define U3D_TQERRIER0		(SSUSB_DEV_BASE + 0x0784)
#define U3D_TQERRIESR0		(SSUSB_DEV_BASE + 0x0788)
#define U3D_TQERRIECR0		(SSUSB_DEV_BASE + 0x078C)
#define U3D_RQERRIR0		(SSUSB_DEV_BASE + 0x07C0)
#define U3D_RQERRIER0		(SSUSB_DEV_BASE + 0x07C4)
#define U3D_RQERRIESR0		(SSUSB_DEV_BASE + 0x07C8)
#define U3D_RQERRIECR0		(SSUSB_DEV_BASE + 0x07CC)
#define U3D_RQERRIR1		(SSUSB_DEV_BASE + 0x07D0)
#define U3D_RQERRIER1		(SSUSB_DEV_BASE + 0x07D4)
#define U3D_RQERRIESR1		(SSUSB_DEV_BASE + 0x07D8)
#define U3D_RQERRIECR1		(SSUSB_DEV_BASE + 0x07DC)

#define U3D_CAP_EP0FFSZ		(SSUSB_DEV_BASE + 0x0C04)
#define U3D_CAP_EPNTXFFSZ	(SSUSB_DEV_BASE + 0x0C08)
#define U3D_CAP_EPNRXFFSZ	(SSUSB_DEV_BASE + 0x0C0C)
#define U3D_CAP_EPINFO		(SSUSB_DEV_BASE + 0x0C10)
#define U3D_MISC_CTRL		(SSUSB_DEV_BASE + 0x0C84)

/*---------------- SSUSB_DEV FIELD DEFINITION ---------------*/

/* U3D_LV1ISR */
#define EP_CTRL_INTR		BIT(5)
#define MAC2_INTR		BIT(4)
#define DMA_INTR		BIT(3)
#define MAC3_INTR		BIT(2)

Annotation

Implementation Notes