drivers/usb/serial/io_16654.h

Source file repositories/reference/linux-study-clean/drivers/usb/serial/io_16654.h

File Facts

System
Linux kernel
Corpus path
drivers/usb/serial/io_16654.h
Extension
.h
Size
7771 bytes
Lines
193
Domain
Driver Families
Bucket
drivers/usb
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#if !defined(_16654_H)
#define	_16654_H

/************************************************************************
 *
 *			D e f i n e s   /   T y p e d e f s
 *
 ************************************************************************/

	//
	// UART register numbers
	// Numbers 0-7 are passed to the Edgeport directly. Numbers 8 and
	// above are used internally to indicate that we must enable access
	// to them via LCR bit 0x80 or LCR = 0xBF.
	// The register number sent to the Edgeport is then (x & 0x7).
	//
	// Driver must not access registers that affect operation of the
	// the EdgePort firmware -- that includes THR, RHR, IER, FCR.


#define THR			0	// ! Transmit Holding Register (Write)
#define RDR			0	// ! Receive Holding Register (Read)
#define IER			1	// ! Interrupt Enable Register
#define FCR			2	// ! Fifo Control Register (Write)
#define ISR			2	// Interrupt Status Register (Read)
#define LCR			3	// Line Control Register
#define MCR			4	// Modem Control Register
#define LSR			5	// Line Status Register
#define MSR			6	// Modem Status Register
#define SPR			7	// ScratchPad Register
#define DLL			8	// Bank2[ 0 ] Divisor Latch LSB
#define DLM			9	// Bank2[ 1 ] Divisor Latch MSB
#define EFR			10	// Bank2[ 2 ] Extended Function Register
//efine unused			11	// Bank2[ 3 ]
#define XON1			12	// Bank2[ 4 ] Xon-1
#define XON2			13	// Bank2[ 5 ] Xon-2
#define XOFF1			14	// Bank2[ 6 ] Xoff-1
#define XOFF2			15	// Bank2[ 7 ] Xoff-2

#define	NUM_16654_REGS		16

#define IS_REG_2ND_BANK(x)	((x) >= 8)

	//
	// Bit definitions for each register
	//

#define IER_RX			0x01	// Enable receive interrupt
#define IER_TX			0x02	// Enable transmit interrupt
#define IER_RXS			0x04	// Enable receive status interrupt
#define IER_MDM			0x08	// Enable modem status interrupt
#define IER_SLEEP		0x10	// Enable sleep mode
#define IER_XOFF		0x20	// Enable s/w flow control (XOFF) interrupt
#define IER_RTS			0x40	// Enable RTS interrupt
#define IER_CTS			0x80	// Enable CTS interrupt
#define IER_ENABLE_ALL		0xFF	// Enable all ints


#define FCR_FIFO_EN		0x01	// Enable FIFOs
#define FCR_RXCLR		0x02	// Reset Rx FIFO
#define FCR_TXCLR		0x04	// Reset Tx FIFO
#define FCR_DMA_BLK		0x08	// Enable DMA block mode
#define FCR_TX_LEVEL_MASK	0x30	// Mask for Tx FIFO Level
#define FCR_TX_LEVEL_8		0x00	// Tx FIFO Level =  8 bytes
#define FCR_TX_LEVEL_16		0x10	// Tx FIFO Level = 16 bytes
#define FCR_TX_LEVEL_32		0x20	// Tx FIFO Level = 32 bytes
#define FCR_TX_LEVEL_56		0x30	// Tx FIFO Level = 56 bytes
#define FCR_RX_LEVEL_MASK	0xC0	// Mask for Rx FIFO Level
#define FCR_RX_LEVEL_8		0x00	// Rx FIFO Level =  8 bytes
#define FCR_RX_LEVEL_16		0x40	// Rx FIFO Level = 16 bytes
#define FCR_RX_LEVEL_56		0x80	// Rx FIFO Level = 56 bytes
#define FCR_RX_LEVEL_60		0xC0	// Rx FIFO Level = 60 bytes


#define ISR_INT_MDM_STATUS	0x00	// Modem status int pending
#define ISR_INT_NONE		0x01	// No interrupt pending
#define ISR_INT_TXRDY		0x02	// Tx ready int pending
#define ISR_INT_RXRDY		0x04	// Rx ready int pending
#define ISR_INT_LINE_STATUS	0x06	// Line status int pending
#define ISR_INT_RX_TIMEOUT	0x0C	// Rx timeout int pending
#define ISR_INT_RX_XOFF		0x10	// Rx Xoff int pending
#define ISR_INT_RTS_CTS		0x20	// RTS/CTS change int pending
#define ISR_FIFO_ENABLED	0xC0	// Bits set if FIFOs enabled
#define ISR_INT_BITS_MASK	0x3E	// Mask to isolate valid int causes


#define LCR_BITS_5		0x00	// 5 bits/char
#define LCR_BITS_6		0x01	// 6 bits/char
#define LCR_BITS_7		0x02	// 7 bits/char
#define LCR_BITS_8		0x03	// 8 bits/char

Annotation

Implementation Notes