drivers/video/fbdev/core/svgalib.c

Source file repositories/reference/linux-study-clean/drivers/video/fbdev/core/svgalib.c

File Facts

System
Linux kernel
Corpus path
drivers/video/fbdev/core/svgalib.c
Extension
.c
Size
20508 bytes
Lines
665
Domain
Driver Families
Bucket
drivers/video
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

while (bitnum <= regset->highbit) {
			bitval = 1 << bitnum;
			regval = regval & ~bitval;
			if (value & 1)
				regval = regval | bitval;
			bitnum++;
			value = value >> 1;
		}
		vga_wcrt(regbase, regset->regnum, regval);
		regset++;
	}
}

/* Write a sequencer register value spread across multiple registers */
void svga_wseq_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value)
{
	u8 regval, bitval, bitnum;

	while (regset->regnum != VGA_REGSET_END_VAL) {
		regval = vga_rseq(regbase, regset->regnum);
		bitnum = regset->lowbit;
		while (bitnum <= regset->highbit) {
			bitval = 1 << bitnum;
			regval = regval & ~bitval;
			if (value & 1)
				regval = regval | bitval;
			bitnum++;
			value = value >> 1;
		}
		vga_wseq(regbase, regset->regnum, regval);
		regset++;
	}
}

static unsigned int svga_regset_size(const struct vga_regset *regset)
{
	u8 count = 0;

	while (regset->regnum != VGA_REGSET_END_VAL) {
		count += regset->highbit - regset->lowbit + 1;
		regset++;
	}
	return 1 << count;
}

/* ------------------------------------------------------------------------- */

/* Set graphics controller registers to sane values */
void svga_set_default_gfx_regs(void __iomem *regbase)
{
	/* All standard GFX registers (GR00 - GR08) */
	vga_wgfx(regbase, VGA_GFX_SR_VALUE, 0x00);
	vga_wgfx(regbase, VGA_GFX_SR_ENABLE, 0x00);
	vga_wgfx(regbase, VGA_GFX_COMPARE_VALUE, 0x00);
	vga_wgfx(regbase, VGA_GFX_DATA_ROTATE, 0x00);
	vga_wgfx(regbase, VGA_GFX_PLANE_READ, 0x00);
	vga_wgfx(regbase, VGA_GFX_MODE, 0x00);
/*	vga_wgfx(regbase, VGA_GFX_MODE, 0x20); */
/*	vga_wgfx(regbase, VGA_GFX_MODE, 0x40); */
	vga_wgfx(regbase, VGA_GFX_MISC, 0x05);
/*	vga_wgfx(regbase, VGA_GFX_MISC, 0x01); */
	vga_wgfx(regbase, VGA_GFX_COMPARE_MASK, 0x0F);
	vga_wgfx(regbase, VGA_GFX_BIT_MASK, 0xFF);
}

/* Set attribute controller registers to sane values */
void svga_set_default_atc_regs(void __iomem *regbase)
{
	u8 count;

	vga_r(regbase, 0x3DA);
	vga_w(regbase, VGA_ATT_W, 0x00);

	/* All standard ATC registers (AR00 - AR14) */
	for (count = 0; count <= 0xF; count++)
		svga_wattr(regbase, count, count);

	svga_wattr(regbase, VGA_ATC_MODE, 0x01);
/*	svga_wattr(regbase, VGA_ATC_MODE, 0x41); */
	svga_wattr(regbase, VGA_ATC_OVERSCAN, 0x00);
	svga_wattr(regbase, VGA_ATC_PLANE_ENABLE, 0x0F);
	svga_wattr(regbase, VGA_ATC_PEL, 0x00);
	svga_wattr(regbase, VGA_ATC_COLOR_PAGE, 0x00);

	vga_r(regbase, 0x3DA);
	vga_w(regbase, VGA_ATT_W, 0x20);
}

/* Set sequencer registers to sane values */
void svga_set_default_seq_regs(void __iomem *regbase)

Annotation

Implementation Notes