drivers/video/fbdev/kyro/STG4000Ramdac.c

Source file repositories/reference/linux-study-clean/drivers/video/fbdev/kyro/STG4000Ramdac.c

File Facts

System
Linux kernel
Corpus path
drivers/video/fbdev/kyro/STG4000Ramdac.c
Extension
.c
Size
3931 bytes
Lines
164
Domain
Driver Families
Bucket
drivers/video
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <video/kyro.h>

#include "STG4000Reg.h"
#include "STG4000Interface.h"

static u32 STG_PIXEL_BUS_WIDTH = 128;	/* 128 bit bus width      */
static u32 REF_CLOCK = 14318;

int InitialiseRamdac(volatile STG4000REG __iomem * pSTGReg,
		     u32 displayDepth,
		     u32 displayWidth,
		     u32 displayHeight,
		     s32 HSyncPolarity,
		     s32 VSyncPolarity, u32 * pixelClock)
{
	u32 tmp = 0;
	u32 F = 0, R = 0, P = 0;
	u32 stride = 0;
	u32 ulPdiv = 0;
	u32 physicalPixelDepth = 0;
	/* Make sure DAC is in Reset */
	tmp = STG_READ_REG(SoftwareReset);

	if (tmp & 0x1) {
		CLEAR_BIT(1);
		STG_WRITE_REG(SoftwareReset, tmp);
	}

	/* Set Pixel Format */
	tmp = STG_READ_REG(DACPixelFormat);
	CLEAR_BITS_FRM_TO(0, 2);

	/* Set LUT not used from 16bpp to 32 bpp ??? */
	CLEAR_BITS_FRM_TO(8, 9);

	switch (displayDepth) {
	case 16:
		{
			physicalPixelDepth = 16;
			tmp |= _16BPP;
			break;
		}
	case 32:
		{
			/* Set for 32 bits per pixel */
			physicalPixelDepth = 32;
			tmp |= _32BPP;
			break;
		}
	default:
		return -EINVAL;
	}

	STG_WRITE_REG(DACPixelFormat, tmp);

	/* Workout Bus transfer bandwidth according to pixel format */
	ulPdiv = STG_PIXEL_BUS_WIDTH / physicalPixelDepth;

	/* Get Screen Stride in pixels */
	stride = displayWidth;

	/* Set Primary size info */
	tmp = STG_READ_REG(DACPrimSize);
	CLEAR_BITS_FRM_TO(0, 10);
	CLEAR_BITS_FRM_TO(12, 31);
	tmp |=
	    ((((displayHeight - 1) << 12) | (((displayWidth / ulPdiv) -
					      1) << 23))
	     | (stride / ulPdiv));
	STG_WRITE_REG(DACPrimSize, tmp);


	/* Set Pixel Clock */
	*pixelClock = ProgramClock(REF_CLOCK, *pixelClock, &F, &R, &P);

	/* Set DAC PLL Mode */
	tmp = STG_READ_REG(DACPLLMode);
	CLEAR_BITS_FRM_TO(0, 15);
	/* tmp |= ((P-1) | ((F-2) << 2) | ((R-2) << 11)); */
	tmp |= ((P) | ((F - 2) << 2) | ((R - 2) << 11));
	STG_WRITE_REG(DACPLLMode, tmp);

	/* Set Prim Address */
	tmp = STG_READ_REG(DACPrimAddress);
	CLEAR_BITS_FRM_TO(0, 20);
	CLEAR_BITS_FRM_TO(20, 31);
	STG_WRITE_REG(DACPrimAddress, tmp);

Annotation

Implementation Notes