drivers/video/fbdev/mb862xx/mb862xx_reg.h
Source file repositories/reference/linux-study-clean/drivers/video/fbdev/mb862xx/mb862xx_reg.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/video/fbdev/mb862xx/mb862xx_reg.h- Extension
.h- Size
- 5538 bytes
- Lines
- 190
- Domain
- Driver Families
- Bucket
- drivers/video
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _MB862XX_REG_H
#define _MB862XX_REG_H
#define MB862XX_MMIO_BASE 0x01fc0000
#define MB862XX_MMIO_HIGH_BASE 0x03fc0000
#define MB862XX_I2C_BASE 0x0000c000
#define MB862XX_DISP_BASE 0x00010000
#define MB862XX_CAP_BASE 0x00018000
#define MB862XX_DRAW_BASE 0x00030000
#define MB862XX_GEO_BASE 0x00038000
#define MB862XX_PIO_BASE 0x00038000
#define MB862XX_MMIO_SIZE 0x40000
/* Host interface/pio registers */
#define GC_IST 0x00000020
#define GC_IMASK 0x00000024
#define GC_SRST 0x0000002c
#define GC_CCF 0x00000038
#define GC_RSW 0x0000005c
#define GC_CID 0x000000f0
#define GC_REVISION 0x00000084
#define GC_CCF_CGE_100 0x00000000
#define GC_CCF_CGE_133 0x00040000
#define GC_CCF_CGE_166 0x00080000
#define GC_CCF_COT_100 0x00000000
#define GC_CCF_COT_133 0x00010000
#define GC_CID_CNAME_MSK 0x0000ff00
#define GC_CID_VERSION_MSK 0x000000ff
/* define enabled interrupts hereby */
#define GC_INT_EN 0x00000000
/* Memory interface mode register */
#define GC_MMR 0x0000fffc
/* Display Controller registers */
#define GC_DCM0 0x00000000
#define GC_HTP 0x00000004
#define GC_HDB_HDP 0x00000008
#define GC_VSW_HSW_HSP 0x0000000c
#define GC_VTR 0x00000010
#define GC_VDP_VSP 0x00000014
#define GC_WY_WX 0x00000018
#define GC_WH_WW 0x0000001c
#define GC_L0M 0x00000020
#define GC_L0OA0 0x00000024
#define GC_L0DA0 0x00000028
#define GC_L0DY_L0DX 0x0000002c
#define GC_L1M 0x00000030
#define GC_L1DA 0x00000034
#define GC_DCM1 0x00000100
#define GC_L0EM 0x00000110
#define GC_L0WY_L0WX 0x00000114
#define GC_L0WH_L0WW 0x00000118
#define GC_L1EM 0x00000120
#define GC_L1WY_L1WX 0x00000124
#define GC_L1WH_L1WW 0x00000128
#define GC_DLS 0x00000180
#define GC_DCM2 0x00000104
#define GC_DCM3 0x00000108
#define GC_CPM_CUTC 0x000000a0
#define GC_CUOA0 0x000000a4
#define GC_CUY0_CUX0 0x000000a8
#define GC_CUOA1 0x000000ac
#define GC_CUY1_CUX1 0x000000b0
#define GC_L0PAL0 0x00000400
#define GC_CPM_CEN0 0x00100000
#define GC_CPM_CEN1 0x00200000
#define GC_DCM1_DEN 0x80000000
#define GC_DCM1_L1E 0x00020000
#define GC_L1M_16 0x80000000
#define GC_L1M_YC 0x40000000
#define GC_L1M_CS 0x20000000
#define GC_DCM01_ESY 0x00000004
#define GC_DCM01_SC 0x00003f00
#define GC_DCM01_RESV 0x00004000
#define GC_DCM01_CKS 0x00008000
#define GC_DCM01_L0E 0x00010000
#define GC_DCM01_DEN 0x80000000
#define GC_L0M_L0C_8 0x00000000
#define GC_L0M_L0C_16 0x80000000
#define GC_L0EM_L0EC_24 0x40000000
#define GC_L0M_L0W_UNIT 64
#define GC_L1EM_DM 0x02000000
#define GC_DISP_REFCLK_400 400
Annotation
- Atlas domain: Driver Families / drivers/video.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.