drivers/video/fbdev/omap2/omapfb/dss/dispc.h

File Facts

System

Linux kernel

Corpus path

drivers/video/fbdev/omap2/omapfb/dss/dispc.h

Extension

.h

Size

17433 bytes

Lines

908

Domain

Driver Families

Bucket

drivers/video

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• struct dispc_coef
• function DISPC_DEFAULT_COLOR
• function DISPC_TRANS_COLOR
• function DISPC_TIMING_H
• function DISPC_TIMING_V
• function DISPC_POL_FREQ
• function DISPC_DIVISORo
• function DISPC_SIZE_MGR
• function DISPC_DATA_CYCLE1
• function DISPC_DATA_CYCLE2
• function DISPC_DATA_CYCLE3
• function DISPC_CPR_COEF_R
• function DISPC_CPR_COEF_G
• function DISPC_CPR_COEF_B
• function DISPC_OVL_BASE
• function DISPC_BA0_OFFSET
• function DISPC_BA1_OFFSET
• function DISPC_BA0_UV_OFFSET
• function DISPC_BA1_UV_OFFSET
• function DISPC_POS_OFFSET
• function DISPC_SIZE_OFFSET
• function DISPC_ATTR_OFFSET
• function DISPC_ATTR2_OFFSET
• function DISPC_FIFO_THRESH_OFFSET
• function DISPC_FIFO_SIZE_STATUS_OFFSET
• function DISPC_ROW_INC_OFFSET
• function DISPC_PIX_INC_OFFSET
• function DISPC_WINDOW_SKIP_OFFSET
• function DISPC_TABLE_BA_OFFSET
• function DISPC_FIR_OFFSET
• function DISPC_FIR2_OFFSET
• function DISPC_PIC_SIZE_OFFSET
• function DISPC_ACCU0_OFFSET
• function DISPC_ACCU2_0_OFFSET
• function DISPC_ACCU1_OFFSET
• function DISPC_ACCU2_1_OFFSET
• function DISPC_FIR_COEF_H_OFFSET
• function DISPC_FIR_COEF_H2_OFFSET
• function DISPC_FIR_COEF_HV_OFFSET
• function DISPC_FIR_COEF_HV2_OFFSET
• function DISPC_CONV_COEF_OFFSET
• function DISPC_FIR_COEF_V_OFFSET
• function DISPC_FIR_COEF_V2_OFFSET
• function DISPC_PRELOAD_OFFSET
• function DISPC_MFLAG_THRESHOLD_OFFSET

Annotated Snippet

struct dispc_coef {
	s8 hc4_vc22;
	s8 hc3_vc2;
	u8 hc2_vc1;
	s8 hc1_vc0;
	s8 hc0_vc00;
};

const struct dispc_coef *dispc_ovl_get_scale_coef(int inc, int five_taps);

/* DISPC manager/channel specific registers */
static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
{
	switch (channel) {
	case OMAP_DSS_CHANNEL_LCD:
		return 0x004C;
	case OMAP_DSS_CHANNEL_DIGIT:
		return 0x0050;
	case OMAP_DSS_CHANNEL_LCD2:
		return 0x03AC;
	case OMAP_DSS_CHANNEL_LCD3:
		return 0x0814;
	default:
		BUG();
		return 0;
	}
}

static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
{
	switch (channel) {
	case OMAP_DSS_CHANNEL_LCD:
		return 0x0054;
	case OMAP_DSS_CHANNEL_DIGIT:
		return 0x0058;
	case OMAP_DSS_CHANNEL_LCD2:
		return 0x03B0;
	case OMAP_DSS_CHANNEL_LCD3:
		return 0x0818;
	default:
		BUG();
		return 0;
	}
}

static inline u16 DISPC_TIMING_H(enum omap_channel channel)
{
	switch (channel) {
	case OMAP_DSS_CHANNEL_LCD:
		return 0x0064;
	case OMAP_DSS_CHANNEL_DIGIT:
		BUG();
		return 0;
	case OMAP_DSS_CHANNEL_LCD2:
		return 0x0400;
	case OMAP_DSS_CHANNEL_LCD3:
		return 0x0840;
	default:
		BUG();
		return 0;
	}
}

static inline u16 DISPC_TIMING_V(enum omap_channel channel)
{
	switch (channel) {
	case OMAP_DSS_CHANNEL_LCD:
		return 0x0068;
	case OMAP_DSS_CHANNEL_DIGIT:
		BUG();
		return 0;
	case OMAP_DSS_CHANNEL_LCD2:
		return 0x0404;
	case OMAP_DSS_CHANNEL_LCD3:
		return 0x0844;
	default:
		BUG();
		return 0;
	}
}

static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
{
	switch (channel) {
	case OMAP_DSS_CHANNEL_LCD:
		return 0x006C;
	case OMAP_DSS_CHANNEL_DIGIT:
		BUG();
		return 0;
	case OMAP_DSS_CHANNEL_LCD2:

Annotation

• Detected declarations: `struct dispc_coef`, `function DISPC_DEFAULT_COLOR`, `function DISPC_TRANS_COLOR`, `function DISPC_TIMING_H`, `function DISPC_TIMING_V`, `function DISPC_POL_FREQ`, `function DISPC_DIVISORo`, `function DISPC_SIZE_MGR`, `function DISPC_DATA_CYCLE1`, `function DISPC_DATA_CYCLE2`.
• Atlas domain: Driver Families / drivers/video.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.