drivers/video/fbdev/pxa3xx-regs.h

Source file repositories/reference/linux-study-clean/drivers/video/fbdev/pxa3xx-regs.h

File Facts

System
Linux kernel
Corpus path
drivers/video/fbdev/pxa3xx-regs.h
Extension
.h
Size
8437 bytes
Lines
181
Domain
Driver Families
Bucket
drivers/video
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __ASM_ARCH_REGS_LCD_H
#define __ASM_ARCH_REGS_LCD_H

/*
 * LCD Controller Registers and Bits Definitions
 */
#define LCCR0		(0x000)	/* LCD Controller Control Register 0 */
#define LCCR1		(0x004)	/* LCD Controller Control Register 1 */
#define LCCR2		(0x008)	/* LCD Controller Control Register 2 */
#define LCCR3		(0x00C)	/* LCD Controller Control Register 3 */
#define LCCR4		(0x010)	/* LCD Controller Control Register 4 */
#define LCCR5		(0x014)	/* LCD Controller Control Register 5 */
#define LCSR		(0x038)	/* LCD Controller Status Register 0 */
#define LCSR1		(0x034)	/* LCD Controller Status Register 1 */
#define LIIDR		(0x03C)	/* LCD Controller Interrupt ID Register */
#define TMEDRGBR	(0x040)	/* TMED RGB Seed Register */
#define TMEDCR		(0x044)	/* TMED Control Register */

#define FBR0		(0x020)	/* DMA Channel 0 Frame Branch Register */
#define FBR1		(0x024)	/* DMA Channel 1 Frame Branch Register */
#define FBR2		(0x028) /* DMA Channel 2 Frame Branch Register */
#define FBR3		(0x02C) /* DMA Channel 2 Frame Branch Register */
#define FBR4		(0x030) /* DMA Channel 2 Frame Branch Register */
#define FBR5		(0x110) /* DMA Channel 2 Frame Branch Register */
#define FBR6		(0x114) /* DMA Channel 2 Frame Branch Register */

#define OVL1C1		(0x050)	/* Overlay 1 Control Register 1 */
#define OVL1C2		(0x060)	/* Overlay 1 Control Register 2 */
#define OVL2C1		(0x070)	/* Overlay 2 Control Register 1 */
#define OVL2C2		(0x080)	/* Overlay 2 Control Register 2 */

#define CMDCR		(0x100)	/* Command Control Register */
#define PRSR		(0x104)	/* Panel Read Status Register */

#define LCCR3_BPP(x)	((((x) & 0x7) << 24) | (((x) & 0x8) ? (1 << 29) : 0))

#define LCCR3_PDFOR_0	(0 << 30)
#define LCCR3_PDFOR_1	(1 << 30)
#define LCCR3_PDFOR_2	(2 << 30)
#define LCCR3_PDFOR_3	(3 << 30)

#define LCCR4_PAL_FOR_0	(0 << 15)
#define LCCR4_PAL_FOR_1	(1 << 15)
#define LCCR4_PAL_FOR_2	(2 << 15)
#define LCCR4_PAL_FOR_3	(3 << 15)
#define LCCR4_PAL_FOR_MASK	(3 << 15)

#define FDADR0		(0x200)	/* DMA Channel 0 Frame Descriptor Address Register */
#define FDADR1		(0x210)	/* DMA Channel 1 Frame Descriptor Address Register */
#define FDADR2		(0x220)	/* DMA Channel 2 Frame Descriptor Address Register */
#define FDADR3		(0x230)	/* DMA Channel 3 Frame Descriptor Address Register */
#define FDADR4		(0x240)	/* DMA Channel 4 Frame Descriptor Address Register */
#define FDADR5		(0x250)	/* DMA Channel 5 Frame Descriptor Address Register */
#define FDADR6		(0x260) /* DMA Channel 6 Frame Descriptor Address Register */

#define LCCR0_ENB	(1 << 0)	/* LCD Controller enable */
#define LCCR0_CMS	(1 << 1)	/* Color/Monochrome Display Select */
#define LCCR0_Color	(LCCR0_CMS*0)	/*  Color display */
#define LCCR0_Mono	(LCCR0_CMS*1)	/*  Monochrome display */
#define LCCR0_SDS	(1 << 2)	/* Single/Dual Panel Display Select */
#define LCCR0_Sngl	(LCCR0_SDS*0)	/*  Single panel display */
#define LCCR0_Dual	(LCCR0_SDS*1)	/*  Dual panel display */

#define LCCR0_LDM	(1 << 3)	/* LCD Disable Done Mask */
#define LCCR0_SFM	(1 << 4)	/* Start of frame mask */
#define LCCR0_IUM	(1 << 5)	/* Input FIFO underrun mask */
#define LCCR0_EFM	(1 << 6)	/* End of Frame mask */
#define LCCR0_PAS	(1 << 7)	/* Passive/Active display Select */
#define LCCR0_Pas	(LCCR0_PAS*0)	/*  Passive display (STN) */
#define LCCR0_Act	(LCCR0_PAS*1)	/*  Active display (TFT) */
#define LCCR0_DPD	(1 << 9)	/* Double Pixel Data (monochrome) */
#define LCCR0_4PixMono	(LCCR0_DPD*0)	/*  4-Pixel/clock Monochrome display */
#define LCCR0_8PixMono	(LCCR0_DPD*1)	/*  8-Pixel/clock Monochrome display */
#define LCCR0_DIS	(1 << 10)	/* LCD Disable */
#define LCCR0_QDM	(1 << 11)	/* LCD Quick Disable mask */
#define LCCR0_PDD	(0xff << 12)	/* Palette DMA request delay */
#define LCCR0_PDD_S	12
#define LCCR0_BM	(1 << 20)	/* Branch mask */
#define LCCR0_OUM	(1 << 21)	/* Output FIFO underrun mask */
#define LCCR0_LCDT	(1 << 22)	/* LCD panel type */
#define LCCR0_RDSTM	(1 << 23)	/* Read status interrupt mask */
#define LCCR0_CMDIM	(1 << 24)	/* Command interrupt mask */
#define LCCR0_OUC	(1 << 25)	/* Overlay Underlay control bit */
#define LCCR0_LDDALT	(1 << 26)	/* LDD alternate mapping control */

#define Fld(Size, Shft)	(((Size) << 16) + (Shft))
#define FShft(Field)	((Field) & 0x0000FFFF)

#define LCCR1_PPL	Fld (10, 0)	/* Pixels Per Line - 1 */
#define LCCR1_DisWdth(Pixel)	(((Pixel) - 1) << FShft (LCCR1_PPL))

Annotation

Implementation Notes