drivers/video/fbdev/via/via_clock.c

Source file repositories/reference/linux-study-clean/drivers/video/fbdev/via/via_clock.c

File Facts

System
Linux kernel
Corpus path
drivers/video/fbdev/via/via_clock.c
Extension
.c
Size
8805 bytes
Lines
354
Domain
Driver Families
Bucket
drivers/video
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
 * Copyright 2011 Florian Tobias Schandinat <FlorianSchandinat@gmx.de>
 */
/*
 * clock and PLL management functions
 */

#include <linux/kernel.h>
#include <linux/via-core.h>

#include "via_clock.h"
#include "global.h"
#include "debug.h"

static const char *via_slap = "Please slap VIA Technologies to motivate them "
	"releasing full documentation for your platform!\n";

static inline u32 cle266_encode_pll(struct via_pll_config pll)
{
	return (pll.multiplier << 8)
		| (pll.rshift << 6)
		| pll.divisor;
}

static inline u32 k800_encode_pll(struct via_pll_config pll)
{
	return ((pll.divisor - 2) << 16)
		| (pll.rshift << 10)
		| (pll.multiplier - 2);
}

static inline u32 vx855_encode_pll(struct via_pll_config pll)
{
	return (pll.divisor << 16)
		| (pll.rshift << 10)
		| pll.multiplier;
}

static inline void cle266_set_primary_pll_encoded(u32 data)
{
	via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */
	via_write_reg(VIASR, 0x46, data & 0xFF);
	via_write_reg(VIASR, 0x47, (data >> 8) & 0xFF);
	via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */
}

static inline void k800_set_primary_pll_encoded(u32 data)
{
	via_write_reg_mask(VIASR, 0x40, 0x02, 0x02); /* enable reset */
	via_write_reg(VIASR, 0x44, data & 0xFF);
	via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF);
	via_write_reg(VIASR, 0x46, (data >> 16) & 0xFF);
	via_write_reg_mask(VIASR, 0x40, 0x00, 0x02); /* disable reset */
}

static inline void cle266_set_secondary_pll_encoded(u32 data)
{
	via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */
	via_write_reg(VIASR, 0x44, data & 0xFF);
	via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF);
	via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */
}

static inline void k800_set_secondary_pll_encoded(u32 data)
{
	via_write_reg_mask(VIASR, 0x40, 0x04, 0x04); /* enable reset */
	via_write_reg(VIASR, 0x4A, data & 0xFF);
	via_write_reg(VIASR, 0x4B, (data >> 8) & 0xFF);
	via_write_reg(VIASR, 0x4C, (data >> 16) & 0xFF);
	via_write_reg_mask(VIASR, 0x40, 0x00, 0x04); /* disable reset */
}

static inline void set_engine_pll_encoded(u32 data)
{
	via_write_reg_mask(VIASR, 0x40, 0x01, 0x01); /* enable reset */
	via_write_reg(VIASR, 0x47, data & 0xFF);
	via_write_reg(VIASR, 0x48, (data >> 8) & 0xFF);
	via_write_reg(VIASR, 0x49, (data >> 16) & 0xFF);
	via_write_reg_mask(VIASR, 0x40, 0x00, 0x01); /* disable reset */
}

static void cle266_set_primary_pll(struct via_pll_config config)
{
	cle266_set_primary_pll_encoded(cle266_encode_pll(config));
}

static void k800_set_primary_pll(struct via_pll_config config)

Annotation

Implementation Notes