drivers/w1/masters/sgi_w1.c
Source file repositories/reference/linux-study-clean/drivers/w1/masters/sgi_w1.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/w1/masters/sgi_w1.c- Extension
.c- Size
- 2754 bytes
- Lines
- 127
- Domain
- Driver Families
- Bucket
- drivers/w1
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/clk.hlinux/delay.hlinux/io.hlinux/jiffies.hlinux/module.hlinux/mod_devicetable.hlinux/platform_device.hlinux/platform_data/sgi-w1.hlinux/w1.h
Detected Declarations
struct sgi_w1_devicefunction sgi_w1_waitfunction sgi_w1_reset_busfunction sgi_w1_touch_bitfunction sgi_w1_probefunction sgi_w1_remove
Annotated Snippet
struct sgi_w1_device {
u32 __iomem *mcr;
struct w1_bus_master bus_master;
char dev_id[64];
};
static u8 sgi_w1_wait(u32 __iomem *mcr)
{
u32 mcr_val;
do {
mcr_val = readl(mcr);
} while (!(mcr_val & MCR_DONE));
return (mcr_val & MCR_RD_DATA) ? 1 : 0;
}
/*
* this is the low level routine to
* reset the device on the One Wire interface
* on the hardware
*/
static u8 sgi_w1_reset_bus(void *data)
{
struct sgi_w1_device *dev = data;
u8 ret;
writel(MCR_PACK(520, 65), dev->mcr);
ret = sgi_w1_wait(dev->mcr);
udelay(500); /* recovery time */
return ret;
}
/*
* this is the low level routine to read/write a bit on the One Wire
* interface on the hardware. It does write 0 if parameter bit is set
* to 0, otherwise a write 1/read.
*/
static u8 sgi_w1_touch_bit(void *data, u8 bit)
{
struct sgi_w1_device *dev = data;
u8 ret;
if (bit)
writel(MCR_PACK(6, 13), dev->mcr);
else
writel(MCR_PACK(80, 30), dev->mcr);
ret = sgi_w1_wait(dev->mcr);
if (bit)
udelay(100); /* recovery */
return ret;
}
static int sgi_w1_probe(struct platform_device *pdev)
{
struct sgi_w1_device *sdev;
struct sgi_w1_platform_data *pdata;
sdev = devm_kzalloc(&pdev->dev, sizeof(struct sgi_w1_device),
GFP_KERNEL);
if (!sdev)
return -ENOMEM;
sdev->mcr = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(sdev->mcr))
return PTR_ERR(sdev->mcr);
sdev->bus_master.data = sdev;
sdev->bus_master.reset_bus = sgi_w1_reset_bus;
sdev->bus_master.touch_bit = sgi_w1_touch_bit;
pdata = dev_get_platdata(&pdev->dev);
if (pdata) {
strscpy(sdev->dev_id, pdata->dev_id, sizeof(sdev->dev_id));
sdev->bus_master.dev_id = sdev->dev_id;
}
platform_set_drvdata(pdev, sdev);
return w1_add_master_device(&sdev->bus_master);
}
/*
* disassociate the w1 device from the driver
*/
static void sgi_w1_remove(struct platform_device *pdev)
{
struct sgi_w1_device *sdev = platform_get_drvdata(pdev);
Annotation
- Immediate include surface: `linux/clk.h`, `linux/delay.h`, `linux/io.h`, `linux/jiffies.h`, `linux/module.h`, `linux/mod_devicetable.h`, `linux/platform_device.h`, `linux/platform_data/sgi-w1.h`.
- Detected declarations: `struct sgi_w1_device`, `function sgi_w1_wait`, `function sgi_w1_reset_bus`, `function sgi_w1_touch_bit`, `function sgi_w1_probe`, `function sgi_w1_remove`.
- Atlas domain: Driver Families / drivers/w1.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.