include/drm/intel/mchbar_regs.h

Source file repositories/reference/linux-study-clean/include/drm/intel/mchbar_regs.h

File Facts

System
Linux kernel
Corpus path
include/drm/intel/mchbar_regs.h
Extension
.h
Size
12340 bytes
Lines
274
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __INTEL_MCHBAR_REGS__
#define __INTEL_MCHBAR_REGS__

#include "i915_reg_defs.h"

/*
 * MCHBAR mirror.
 *
 * This mirrors the MCHBAR MMIO space whose location is determined by
 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
 * every way.  It is not accessible from the CP register read instructions.
 *
 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
 * just read. On MTL+ the mirror no longer exists.
 */

#define MCHBAR_MIRROR_BASE			0x10000
#define MCHBAR_MIRROR_END			0x13fff

#define MCHBAR_MIRROR_BASE_SNB			0x140000
#define MCHBAR_MIRROR_END_SNB			0x147fff
#define MCHBAR_MIRROR_END_ICL_RKL		0x14ffff
#define MCHBAR_MIRROR_END_TGL			0x15ffff

#define CTG_STOLEN_RESERVED			_MMIO(MCHBAR_MIRROR_BASE + 0x34)
#define ELK_STOLEN_RESERVED			_MMIO(MCHBAR_MIRROR_BASE + 0x48)
#define   G4X_STOLEN_RESERVED_ADDR1_MASK	(0xFFFF << 16)
#define   G4X_STOLEN_RESERVED_ADDR2_MASK	(0xFFF << 4)
#define   G4X_STOLEN_RESERVED_ENABLE		(1 << 0)

/* Pineview MCH register contains DDR3 setting */
#define CSHRDDR3CTL				_MMIO(MCHBAR_MIRROR_BASE + 0x1a8)
#define   CSHRDDR3CTL_DDR3			(1 << 2)

/* 915-945 and GM965 MCH register controlling DRAM channel access */
#define DCC					_MMIO(MCHBAR_MIRROR_BASE + 0x200)
#define   DCC_ADDRESSING_MODE_SINGLE_CHANNEL	(0 << 0)
#define   DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC	(1 << 0)
#define   DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED	(2 << 0)
#define   DCC_ADDRESSING_MODE_MASK		(3 << 0)
#define   DCC_CHANNEL_XOR_DISABLE		(1 << 10)
#define   DCC_CHANNEL_XOR_BIT_17		(1 << 9)
#define DCC2					_MMIO(MCHBAR_MIRROR_BASE + 0x204)
#define   DCC2_MODIFIED_ENHANCED_DISABLE	(1 << 20)

/* 965 MCH register controlling DRAM channel configuration */
#define C0DRB3_BW				_MMIO(MCHBAR_MIRROR_BASE + 0x206)
#define C1DRB3_BW				_MMIO(MCHBAR_MIRROR_BASE + 0x606)

/* Clocking configuration register */
#define CLKCFG					_MMIO(MCHBAR_MIRROR_BASE + 0xc00)
#define CLKCFG_FSB_400				(0 << 0)	/* hrawclk 100 */
#define CLKCFG_FSB_400_ALT			(5 << 0)	/* hrawclk 100 */
#define CLKCFG_FSB_533				(1 << 0)	/* hrawclk 133 */
#define CLKCFG_FSB_667				(3 << 0)	/* hrawclk 166 */
#define CLKCFG_FSB_800				(2 << 0)	/* hrawclk 200 */
#define CLKCFG_FSB_1067				(6 << 0)	/* hrawclk 266 */
#define CLKCFG_FSB_1067_ALT			(0 << 0)	/* hrawclk 266 */
#define CLKCFG_FSB_1333				(7 << 0)	/* hrawclk 333 */
#define CLKCFG_FSB_1333_ALT			(4 << 0)	/* hrawclk 333 */
#define CLKCFG_FSB_1600_ALT			(6 << 0)	/* hrawclk 400 */
#define CLKCFG_FSB_MASK				(7 << 0)
#define CLKCFG_MEM_533				(1 << 4)
#define CLKCFG_MEM_667				(2 << 4)
#define CLKCFG_MEM_800				(3 << 4)
#define CLKCFG_MEM_MASK				(7 << 4)

#define HPLLVCO_MOBILE				_MMIO(MCHBAR_MIRROR_BASE + 0xc0f)
#define HPLLVCO					_MMIO(MCHBAR_MIRROR_BASE + 0xc38)

#define TSC1					_MMIO(MCHBAR_MIRROR_BASE + 0x1001)
#define   TSE					(1 << 0)
#define TR1					_MMIO(MCHBAR_MIRROR_BASE + 0x1006)
#define TSFS					_MMIO(MCHBAR_MIRROR_BASE + 0x1020)
#define   TSFS_SLOPE_MASK			0x0000ff00
#define   TSFS_SLOPE_SHIFT			8
#define   TSFS_INTR_MASK			0x000000ff

/* Memory latency timer register */
#define MLTR_ILK				_MMIO(MCHBAR_MIRROR_BASE + 0x1222)
/* the unit of memory self-refresh latency time is 0.5us */
#define   MLTR_WM2_MASK				REG_GENMASK(13, 8)
#define   MLTR_WM1_MASK				REG_GENMASK(5, 0)

#define CSIPLL0					_MMIO(MCHBAR_MIRROR_BASE + 0x2c10)
#define DDRMPLL1				_MMIO(MCHBAR_MIRROR_BASE + 0x2c20)

#define ILK_GDSR				_MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
#define  ILK_GRDOM_FULL				(0 << 1)
#define  ILK_GRDOM_RENDER			(1 << 1)

Annotation

Implementation Notes