include/drm/intel/vlv_iosf_sb_regs.h

Source file repositories/reference/linux-study-clean/include/drm/intel/vlv_iosf_sb_regs.h

File Facts

System
Linux kernel
Corpus path
include/drm/intel/vlv_iosf_sb_regs.h
Extension
.h
Size
7001 bytes
Lines
193
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _VLV_IOSF_SB_REGS_H_
#define _VLV_IOSF_SB_REGS_H_

enum vlv_iosf_sb_unit {
	VLV_IOSF_SB_BUNIT,
	VLV_IOSF_SB_CCK,
	VLV_IOSF_SB_CCU,
	VLV_IOSF_SB_DPIO,
	VLV_IOSF_SB_DPIO_2,
	VLV_IOSF_SB_FLISDSI,
	VLV_IOSF_SB_GPIO,
	VLV_IOSF_SB_NC,
	VLV_IOSF_SB_PUNIT,
};

/* See configdb bunit SB addr map */
#define BUNIT_REG_BISOC				0x11

/* PUNIT_REG_*SSPM0 */
#define   _SSPM0_SSC(val)			((val) << 0)
#define   SSPM0_SSC_MASK			_SSPM0_SSC(0x3)
#define   SSPM0_SSC_PWR_ON			_SSPM0_SSC(0x0)
#define   SSPM0_SSC_CLK_GATE			_SSPM0_SSC(0x1)
#define   SSPM0_SSC_RESET			_SSPM0_SSC(0x2)
#define   SSPM0_SSC_PWR_GATE			_SSPM0_SSC(0x3)
#define   _SSPM0_SSS(val)			((val) << 24)
#define   SSPM0_SSS_MASK			_SSPM0_SSS(0x3)
#define   SSPM0_SSS_PWR_ON			_SSPM0_SSS(0x0)
#define   SSPM0_SSS_CLK_GATE			_SSPM0_SSS(0x1)
#define   SSPM0_SSS_RESET			_SSPM0_SSS(0x2)
#define   SSPM0_SSS_PWR_GATE			_SSPM0_SSS(0x3)

/* PUNIT_REG_*SSPM1 */
#define   SSPM1_FREQSTAT_SHIFT			24
#define   SSPM1_FREQSTAT_MASK			(0x1f << SSPM1_FREQSTAT_SHIFT)
#define   SSPM1_FREQGUAR_SHIFT			8
#define   SSPM1_FREQGUAR_MASK			(0x1f << SSPM1_FREQGUAR_SHIFT)
#define   SSPM1_FREQ_SHIFT			0
#define   SSPM1_FREQ_MASK			(0x1f << SSPM1_FREQ_SHIFT)

#define PUNIT_REG_VEDSSPM0			0x32
#define PUNIT_REG_VEDSSPM1			0x33

#define PUNIT_REG_DSPSSPM			0x36
#define   DSPFREQSTAT_SHIFT_CHV			24
#define   DSPFREQSTAT_MASK_CHV			(0x1f << DSPFREQSTAT_SHIFT_CHV)
#define   DSPFREQGUAR_SHIFT_CHV			8
#define   DSPFREQGUAR_MASK_CHV			(0x1f << DSPFREQGUAR_SHIFT_CHV)
#define   DSPFREQSTAT_SHIFT			30
#define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
#define   DSPFREQGUAR_SHIFT			14
#define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
#define   DSP_MAXFIFO_PM5_STATUS		(1 << 22) /* chv */
#define   DSP_AUTO_CDCLK_GATE_DISABLE		(1 << 7) /* chv */
#define   DSP_MAXFIFO_PM5_ENABLE		(1 << 6) /* chv */
#define   _DP_SSC(val, pipe)			((val) << (2 * (pipe)))
#define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
#define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
#define   DP_SSC_CLK_GATE(pipe)			_DP_SSC(0x1, (pipe))
#define   DP_SSC_RESET(pipe)			_DP_SSC(0x2, (pipe))
#define   DP_SSC_PWR_GATE(pipe)			_DP_SSC(0x3, (pipe))
#define   _DP_SSS(val, pipe)			((val) << (2 * (pipe) + 16))
#define   DP_SSS_MASK(pipe)			_DP_SSS(0x3, (pipe))
#define   DP_SSS_PWR_ON(pipe)			_DP_SSS(0x0, (pipe))
#define   DP_SSS_CLK_GATE(pipe)			_DP_SSS(0x1, (pipe))
#define   DP_SSS_RESET(pipe)			_DP_SSS(0x2, (pipe))
#define   DP_SSS_PWR_GATE(pipe)			_DP_SSS(0x3, (pipe))

#define PUNIT_REG_ISPSSPM0			0x39
#define PUNIT_REG_ISPSSPM1			0x3a

#define PUNIT_REG_PWRGT_CTRL			0x60
#define PUNIT_REG_PWRGT_STATUS			0x61
#define   PUNIT_PWRGT_MASK(pw_idx)		(3 << ((pw_idx) * 2))
#define   PUNIT_PWRGT_PWR_ON(pw_idx)		(0 << ((pw_idx) * 2))
#define   PUNIT_PWRGT_CLK_GATE(pw_idx)		(1 << ((pw_idx) * 2))
#define   PUNIT_PWRGT_RESET(pw_idx)		(2 << ((pw_idx) * 2))
#define   PUNIT_PWRGT_PWR_GATE(pw_idx)		(3 << ((pw_idx) * 2))

#define PUNIT_PWGT_IDX_RENDER			0
#define PUNIT_PWGT_IDX_MEDIA			1
#define PUNIT_PWGT_IDX_DISP2D			3
#define PUNIT_PWGT_IDX_DPIO_CMN_BC		5
#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01	6
#define PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23	7
#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01	8
#define PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23	9
#define PUNIT_PWGT_IDX_DPIO_RX0			10
#define PUNIT_PWGT_IDX_DPIO_RX1			11
#define PUNIT_PWGT_IDX_DPIO_CMN_D		12

Annotation

Implementation Notes