include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h
Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h
File Facts
- System
- Linux kernel
- Corpus path
include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h- Extension
.h- Size
- 7246 bytes
- Lines
- 248
- Domain
- Repository Root And Misc
- Bucket
- include
- Inferred role
- Repository Root And Misc: implementation source
- Status
- source implementation candidate
Why This File Exists
Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
- Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H
#define _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H
#define CLKID_RTC_32K_CLKIN 0
#define CLKID_RTC_32K_DIV 1
#define CLKID_RTC_32K_SEL 2
#define CLKID_RTC_32K_XATL 3
#define CLKID_RTC 4
#define CLKID_SYS_CLK_B_SEL 5
#define CLKID_SYS_CLK_B_DIV 6
#define CLKID_SYS_CLK_B 7
#define CLKID_SYS_CLK_A_SEL 8
#define CLKID_SYS_CLK_A_DIV 9
#define CLKID_SYS_CLK_A 10
#define CLKID_SYS 11
#define CLKID_CECA_32K_CLKIN 12
#define CLKID_CECA_32K_DIV 13
#define CLKID_CECA_32K_SEL_PRE 14
#define CLKID_CECA_32K_SEL 15
#define CLKID_CECA_32K_CLKOUT 16
#define CLKID_CECB_32K_CLKIN 17
#define CLKID_CECB_32K_DIV 18
#define CLKID_CECB_32K_SEL_PRE 19
#define CLKID_CECB_32K_SEL 20
#define CLKID_CECB_32K_CLKOUT 21
#define CLKID_SC_CLK_SEL 22
#define CLKID_SC_CLK_DIV 23
#define CLKID_SC 24
#define CLKID_12_24M 25
#define CLKID_12M_CLK_DIV 26
#define CLKID_12_24M_CLK_SEL 27
#define CLKID_VID_PLL_DIV 28
#define CLKID_VID_PLL_SEL 29
#define CLKID_VID_PLL 30
#define CLKID_VCLK_SEL 31
#define CLKID_VCLK2_SEL 32
#define CLKID_VCLK_INPUT 33
#define CLKID_VCLK2_INPUT 34
#define CLKID_VCLK_DIV 35
#define CLKID_VCLK2_DIV 36
#define CLKID_VCLK 37
#define CLKID_VCLK2 38
#define CLKID_VCLK_DIV1 39
#define CLKID_VCLK_DIV2_EN 40
#define CLKID_VCLK_DIV4_EN 41
#define CLKID_VCLK_DIV6_EN 42
#define CLKID_VCLK_DIV12_EN 43
#define CLKID_VCLK2_DIV1 44
#define CLKID_VCLK2_DIV2_EN 45
#define CLKID_VCLK2_DIV4_EN 46
#define CLKID_VCLK2_DIV6_EN 47
#define CLKID_VCLK2_DIV12_EN 48
#define CLKID_VCLK_DIV2 49
#define CLKID_VCLK_DIV4 50
#define CLKID_VCLK_DIV6 51
#define CLKID_VCLK_DIV12 52
#define CLKID_VCLK2_DIV2 53
#define CLKID_VCLK2_DIV4 54
#define CLKID_VCLK2_DIV6 55
#define CLKID_VCLK2_DIV12 56
#define CLKID_CTS_ENCI_SEL 57
#define CLKID_CTS_ENCP_SEL 58
#define CLKID_CTS_VDAC_SEL 59
#define CLKID_HDMI_TX_SEL 60
#define CLKID_CTS_ENCI 61
#define CLKID_CTS_ENCP 62
#define CLKID_CTS_VDAC 63
#define CLKID_HDMI_TX 64
#define CLKID_HDMI_SEL 65
#define CLKID_HDMI_DIV 66
#define CLKID_HDMI 67
#define CLKID_TS_CLK_DIV 68
#define CLKID_TS 69
#define CLKID_MALI_0_SEL 70
#define CLKID_MALI_0_DIV 71
#define CLKID_MALI_0 72
#define CLKID_MALI_1_SEL 73
#define CLKID_MALI_1_DIV 74
#define CLKID_MALI_1 75
#define CLKID_MALI_SEL 76
#define CLKID_VDEC_P0_SEL 77
#define CLKID_VDEC_P0_DIV 78
#define CLKID_VDEC_P0 79
#define CLKID_VDEC_P1_SEL 80
#define CLKID_VDEC_P1_DIV 81
#define CLKID_VDEC_P1 82
#define CLKID_VDEC_SEL 83
#define CLKID_HEVCF_P0_SEL 84
#define CLKID_HEVCF_P0_DIV 85
#define CLKID_HEVCF_P0 86
Annotation
- Atlas domain: Repository Root And Misc / include.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.