include/dt-bindings/clock/aspeed,ast2700-scu.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/aspeed,ast2700-scu.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/aspeed,ast2700-scu.h
Extension
.h
Size
4890 bytes
Lines
168
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __DT_BINDINGS_CLOCK_AST2700_H
#define __DT_BINDINGS_CLOCK_AST2700_H

/* SOC0 clk */
#define SCU0_CLKIN		0
#define SCU0_CLK_24M		1
#define SCU0_CLK_192M		2
#define SCU0_CLK_UART		3
#define SCU0_CLK_UART_DIV13	3
#define SCU0_CLK_PSP		4
#define SCU0_CLK_HPLL		5
#define SCU0_CLK_HPLL_DIV2	6
#define SCU0_CLK_HPLL_DIV4	7
#define SCU0_CLK_HPLL_DIV_AHB	8
#define SCU0_CLK_DPLL		9
#define SCU0_CLK_MPLL		10
#define SCU0_CLK_MPLL_DIV2	11
#define SCU0_CLK_MPLL_DIV4	12
#define SCU0_CLK_MPLL_DIV8	13
#define SCU0_CLK_MPLL_DIV_AHB	14
#define SCU0_CLK_D0		15
#define SCU0_CLK_D1		16
#define SCU0_CLK_CRT0		17
#define SCU0_CLK_CRT1		18
#define SCU0_CLK_MPHY		19
#define SCU0_CLK_AXI0		20
#define SCU0_CLK_AXI1		21
#define SCU0_CLK_AHB		22
#define SCU0_CLK_APB		23
#define SCU0_CLK_UART4		24
#define SCU0_CLK_EMMCMUX	25
#define SCU0_CLK_EMMC		26
#define SCU0_CLK_U2PHY_CLK12M	27
#define SCU0_CLK_U2PHY_REFCLK	28

/* SOC0 clk-gate */
#define SCU0_CLK_GATE_MCLK	29
#define SCU0_CLK_GATE_ECLK	30
#define SCU0_CLK_GATE_2DCLK	31
#define SCU0_CLK_GATE_VCLK	32
#define SCU0_CLK_GATE_BCLK	33
#define SCU0_CLK_GATE_VGA0CLK	34
#define SCU0_CLK_GATE_REFCLK	35
#define SCU0_CLK_GATE_PORTBUSB2CLK	36
#define SCU0_CLK_GATE_UHCICLK	37
#define SCU0_CLK_GATE_VGA1CLK	38
#define SCU0_CLK_GATE_DDRPHYCLK	39
#define SCU0_CLK_GATE_E2M0CLK	40
#define SCU0_CLK_GATE_HACCLK	41
#define SCU0_CLK_GATE_PORTAUSB2CLK	42
#define SCU0_CLK_GATE_UART4CLK	43
#define SCU0_CLK_GATE_SLICLK	44
#define SCU0_CLK_GATE_DACCLK	45
#define SCU0_CLK_GATE_DP	46
#define SCU0_CLK_GATE_E2M1CLK	47
#define SCU0_CLK_GATE_CRT0CLK	48
#define SCU0_CLK_GATE_CRT1CLK	49
#define SCU0_CLK_GATE_ECDSACLK	50
#define SCU0_CLK_GATE_RSACLK	51
#define SCU0_CLK_GATE_RVAS0CLK	52
#define SCU0_CLK_GATE_UFSCLK	53
#define SCU0_CLK_GATE_EMMCCLK	54
#define SCU0_CLK_GATE_RVAS1CLK	55
#define SCU0_CLK_U2PHY_REFCLKSRC 56
#define SCU0_CLK_AHBMUX			57
#define SCU0_CLK_MPHYSRC		58

/* SOC1 clk */
#define SCU1_CLKIN		0
#define SCU1_CLK_HPLL		1
#define SCU1_CLK_APLL		2
#define SCU1_CLK_APLL_DIV2	3
#define SCU1_CLK_APLL_DIV4	4
#define SCU1_CLK_DPLL		5
#define SCU1_CLK_UXCLK		6
#define SCU1_CLK_HUXCLK		7
#define SCU1_CLK_UARTX		8
#define SCU1_CLK_HUARTX		9
#define SCU1_CLK_AHB		10
#define SCU1_CLK_APB		11
#define SCU1_CLK_UART0		12
#define SCU1_CLK_UART1		13
#define SCU1_CLK_UART2		14
#define SCU1_CLK_UART3		15
#define SCU1_CLK_UART5		16
#define SCU1_CLK_UART6		17
#define SCU1_CLK_UART7		18
#define SCU1_CLK_UART8		19
#define SCU1_CLK_UART9		20
#define SCU1_CLK_UART10		21

Annotation

Implementation Notes