include/dt-bindings/clock/axis,artpec8-clk.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/axis,artpec8-clk.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/axis,artpec8-clk.h
Extension
.h
Size
6301 bytes
Lines
170
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLOCK_ARTPEC8_H
#define _DT_BINDINGS_CLOCK_ARTPEC8_H

/* CMU_CMU */
#define CLK_FOUT_SHARED0_PLL					1
#define CLK_DOUT_SHARED0_DIV2					2
#define CLK_DOUT_SHARED0_DIV3					3
#define CLK_DOUT_SHARED0_DIV4					4
#define CLK_FOUT_SHARED1_PLL					5
#define CLK_DOUT_SHARED1_DIV2					6
#define CLK_DOUT_SHARED1_DIV3					7
#define CLK_DOUT_SHARED1_DIV4					8
#define CLK_FOUT_AUDIO_PLL					9
#define CLK_DOUT_CMU_BUS					10
#define CLK_DOUT_CMU_BUS_DLP					11
#define CLK_DOUT_CMU_CDC_CORE					12
#define CLK_DOUT_CMU_OTP					13
#define CLK_DOUT_CMU_CORE_MAIN					14
#define CLK_DOUT_CMU_CORE_DLP					15
#define CLK_DOUT_CMU_CPUCL_SWITCH				16
#define CLK_DOUT_CMU_DLP_CORE					17
#define CLK_DOUT_CMU_FSYS_BUS					18
#define CLK_DOUT_CMU_FSYS_IP					19
#define CLK_DOUT_CMU_FSYS_SCAN0					20
#define CLK_DOUT_CMU_FSYS_SCAN1					21
#define CLK_DOUT_CMU_GPU_3D					22
#define CLK_DOUT_CMU_GPU_2D					23
#define CLK_DOUT_CMU_IMEM_ACLK					24
#define CLK_DOUT_CMU_IMEM_JPEG					25
#define CLK_DOUT_CMU_MIF_SWITCH					26
#define CLK_DOUT_CMU_MIF_BUSP					27
#define CLK_DOUT_CMU_PERI_DISP					28
#define CLK_DOUT_CMU_PERI_IP					29
#define CLK_DOUT_CMU_PERI_AUDIO					30
#define CLK_DOUT_CMU_RSP_CORE					31
#define CLK_DOUT_CMU_TRFM_CORE					32
#define CLK_DOUT_CMU_VCA_ACE					33
#define CLK_DOUT_CMU_VCA_OD					34
#define CLK_DOUT_CMU_VIO_CORE					35
#define CLK_DOUT_CMU_VIO_AUDIO					36
#define CLK_DOUT_CMU_VIP0_CORE					37
#define CLK_DOUT_CMU_VIP1_CORE					38
#define CLK_DOUT_CMU_VPP_CORE					39

/* CMU_BUS */
#define CLK_MOUT_BUS_ACLK_USER					1
#define CLK_MOUT_BUS_DLP_USER					2
#define CLK_DOUT_BUS_PCLK					3

/* CMU_CORE */
#define CLK_MOUT_CORE_ACLK_USER					1
#define CLK_MOUT_CORE_DLP_USER					2
#define CLK_DOUT_CORE_PCLK					3

/* CMU_CPUCL */
#define CLK_FOUT_CPUCL_PLL					1
#define CLK_MOUT_CPUCL_PLL					2
#define CLK_MOUT_CPUCL_SWITCH_USER				3
#define CLK_DOUT_CPUCL_CPU					4
#define CLK_DOUT_CPUCL_CLUSTER_ACLK				5
#define CLK_DOUT_CPUCL_CLUSTER_PCLKDBG				6
#define CLK_DOUT_CPUCL_CLUSTER_CNTCLK				7
#define CLK_DOUT_CPUCL_CLUSTER_ATCLK				8
#define CLK_DOUT_CPUCL_PCLK					9
#define CLK_DOUT_CPUCL_CMUREF					10
#define CLK_DOUT_CPUCL_DBG					11
#define CLK_DOUT_CPUCL_PCLKDBG					12
#define CLK_GOUT_CPUCL_CLUSTER_CPU				13
#define CLK_GOUT_CPUCL_SHORTSTOP				14
#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG			15
#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK			16

/* CMU_FSYS */
#define CLK_FOUT_FSYS_PLL					1
#define CLK_MOUT_FSYS_SCAN0_USER				2
#define CLK_MOUT_FSYS_SCAN1_USER				3
#define CLK_MOUT_FSYS_BUS_USER					4
#define CLK_MOUT_FSYS_MMC_USER					5
#define CLK_DOUT_FSYS_PCIE_PIPE					6
#define CLK_DOUT_FSYS_ADC					7
#define CLK_DOUT_FSYS_PCIE_PHY_REFCLK_SYSPLL			8
#define CLK_DOUT_FSYS_EQOS_INT125				9
#define CLK_DOUT_FSYS_OTP_MEM					10
#define CLK_DOUT_FSYS_SCLK_UART					11
#define CLK_DOUT_FSYS_EQOS_25					12
#define CLK_DOUT_FSYS_EQOS_2p5					13
#define CLK_DOUT_FSYS_BUS300					14
#define CLK_DOUT_FSYS_BUS_QSPI					15
#define CLK_DOUT_FSYS_MMC_CARD0					16
#define CLK_DOUT_FSYS_MMC_CARD1					17

Annotation

Implementation Notes