include/dt-bindings/clock/axis,artpec9-clk.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/axis,artpec9-clk.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/axis,artpec9-clk.h
Extension
.h
Size
7955 bytes
Lines
196
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLOCK_ARTPEC9_H
#define _DT_BINDINGS_CLOCK_ARTPEC9_H

/* CMU_CMU */
#define CLK_FOUT_SHARED0_PLL						1
#define CLK_DOUT_SHARED0_DIV2						2
#define CLK_DOUT_SHARED0_DIV3						3
#define CLK_DOUT_SHARED0_DIV4						4
#define CLK_FOUT_SHARED1_PLL						5
#define CLK_DOUT_SHARED1_DIV2						6
#define CLK_DOUT_SHARED1_DIV3						7
#define CLK_DOUT_SHARED1_DIV4						8
#define CLK_FOUT_AUDIO_PLL						9
#define CLK_DOUT_CMU_ADD						10
#define CLK_DOUT_CMU_BUS						11
#define CLK_DOUT_CMU_CDC_CORE						12
#define CLK_DOUT_CMU_CORE_MAIN						13
#define CLK_DOUT_CMU_CPUCL_SWITCH					14
#define CLK_DOUT_CMU_DLP_CORE						15
#define CLK_DOUT_CMU_FSYS0_BUS						16
#define CLK_DOUT_CMU_FSYS0_IP						17
#define CLK_DOUT_CMU_FSYS1_BUS						18
#define CLK_DOUT_CMU_FSYS1_SCAN0					19
#define CLK_DOUT_CMU_FSYS1_SCAN1					20
#define CLK_DOUT_CMU_GPU_3D						21
#define CLK_DOUT_CMU_GPU_2D						22
#define CLK_DOUT_CMU_IMEM_ACLK						23
#define CLK_DOUT_CMU_IMEM_CA5						24
#define CLK_DOUT_CMU_IMEM_JPEG						25
#define CLK_DOUT_CMU_IMEM_SSS						26
#define CLK_DOUT_CMU_IPA_CORE						27
#define CLK_DOUT_CMU_LCPU						28
#define CLK_DOUT_CMU_MIF_SWITCH						29
#define CLK_DOUT_CMU_MIF_BUSP						30
#define CLK_DOUT_CMU_PERI_DISP						31
#define CLK_DOUT_CMU_PERI_IP						32
#define CLK_DOUT_CMU_RSP_CORE						33
#define CLK_DOUT_CMU_TRFM						34
#define CLK_DOUT_CMU_VIO_CORE_L						35
#define CLK_DOUT_CMU_VIO_CORE						36
#define CLK_DOUT_CMU_VIP0						37
#define CLK_DOUT_CMU_VIP1						38
#define CLK_DOUT_CMU_VPP_CORE						39
#define CLK_DOUT_CMU_VIO_AUDIO						40

/* CMU_BUS */
#define CLK_MOUT_BUS_ACLK_USER						1

/* CMU_CORE */
#define CLK_MOUT_CORE_ACLK_USER						1

/* CMU_CPUCL */
#define CLK_FOUT_CPUCL_PLL0						1
#define CLK_MOUT_CPUCL_PLL0						2
#define CLK_FOUT_CPUCL_PLL1						3
#define CLK_MOUT_CPUCL_PLL_SCU						4
#define CLK_MOUT_CPUCL_SWITCH_SCU_USER					5
#define CLK_MOUT_CPUCL_SWITCH_USER					6
#define CLK_DOUT_CPUCL_CPU						7
#define CLK_DOUT_CPUCL_CLUSTER_PERIPHCLK				8
#define CLK_DOUT_CPUCL_CLUSTER_GICCLK					9
#define CLK_DOUT_CPUCL_CLUSTER_PCLK					10
#define CLK_DOUT_CPUCL_CMUREF						11
#define CLK_DOUT_CPUCL_CLUSTER_ATCLK					12
#define CLK_DOUT_CPUCL_CLUSTER_SCU					13
#define CLK_DOUT_CPUCL_DBG						14
#define CLK_GOUT_CPUCL_SHORTSTOP					15
#define CLK_GOUT_CPUCL_CLUSTER_CPU					16
#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_ATCLK				17
#define CLK_GOUT_CPUCL_CSSYS_IPCLKPORT_PCLKDBG				18

/* CMU_FSYS0 */
#define CLK_MOUT_FSYS0_BUS_USER						1
#define CLK_MOUT_FSYS0_IP_USER						2
#define CLK_MOUT_FSYS0_MAIN_USER					3
#define CLK_DOUT_FSYS0_125						4
#define CLK_DOUT_FSYS0_ADC						5
#define CLK_DOUT_FSYS0_BUS_300						6
#define CLK_DOUT_FSYS0_EQOS0						7
#define CLK_DOUT_FSYS0_EQOS1						8
#define CLK_DOUT_FSYS0_MMC_CARD0					9
#define CLK_DOUT_FSYS0_MMC_CARD1					10
#define CLK_DOUT_FSYS0_MMC_CARD2					11
#define CLK_DOUT_FSYS0_QSPI						12
#define CLK_DOUT_FSYS0_SFMC_NAND					13
#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I			14
#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_CSR_I			15
#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_I_RGMII_PHASE_CLK_250	16
#define CLK_GOUT_FSYS0_EQOS_TOP0_IPCLKPORT_I_RGMII_TXCLK		17
#define CLK_GOUT_FSYS0_EQOS_TOP1_IPCLKPORT_I_RGMII_PHASE_CLK_250	18

Annotation

Implementation Notes