include/dt-bindings/clock/exynos5420.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/exynos5420.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/exynos5420.h
Extension
.h
Size
7397 bytes
Lines
275
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H
#define _DT_BINDINGS_CLOCK_EXYNOS_5420_H

/* core clocks */
#define CLK_FIN_PLL		1
#define CLK_FOUT_APLL		2
#define CLK_FOUT_CPLL		3
#define CLK_FOUT_DPLL		4
#define CLK_FOUT_EPLL		5
#define CLK_FOUT_RPLL		6
#define CLK_FOUT_IPLL		7
#define CLK_FOUT_SPLL		8
#define CLK_FOUT_VPLL		9
#define CLK_FOUT_MPLL		10
#define CLK_FOUT_BPLL		11
#define CLK_FOUT_KPLL		12
#define CLK_ARM_CLK		13
#define CLK_KFC_CLK		14

/* gate for special clocks (sclk) */
#define CLK_SCLK_UART0		128
#define CLK_SCLK_UART1		129
#define CLK_SCLK_UART2		130
#define CLK_SCLK_UART3		131
#define CLK_SCLK_MMC0		132
#define CLK_SCLK_MMC1		133
#define CLK_SCLK_MMC2		134
#define CLK_SCLK_SPI0		135
#define CLK_SCLK_SPI1		136
#define CLK_SCLK_SPI2		137
#define CLK_SCLK_I2S1		138
#define CLK_SCLK_I2S2		139
#define CLK_SCLK_PCM1		140
#define CLK_SCLK_PCM2		141
#define CLK_SCLK_SPDIF		142
#define CLK_SCLK_HDMI		143
#define CLK_SCLK_PIXEL		144
#define CLK_SCLK_DP1		145
#define CLK_SCLK_MIPI1		146
#define CLK_SCLK_FIMD1		147
#define CLK_SCLK_MAUDIO0	148
#define CLK_SCLK_MAUPCM0	149
#define CLK_SCLK_USBD300	150
#define CLK_SCLK_USBD301	151
#define CLK_SCLK_USBPHY300	152
#define CLK_SCLK_USBPHY301	153
#define CLK_SCLK_UNIPRO		154
#define CLK_SCLK_PWM		155
#define CLK_SCLK_GSCL_WA	156
#define CLK_SCLK_GSCL_WB	157
#define CLK_SCLK_HDMIPHY	158
#define CLK_MAU_EPLL		159
#define CLK_SCLK_HSIC_12M	160
#define CLK_SCLK_MPHY_IXTAL24	161
#define CLK_SCLK_BPLL		162

/* gate clocks */
#define CLK_UART0		257
#define CLK_UART1		258
#define CLK_UART2		259
#define CLK_UART3		260
#define CLK_I2C0		261
#define CLK_I2C1		262
#define CLK_I2C2		263
#define CLK_I2C3		264
#define CLK_USI0		265
#define CLK_USI1		266
#define CLK_USI2		267
#define CLK_USI3		268
#define CLK_I2C_HDMI		269
#define CLK_TSADC		270
#define CLK_SPI0		271
#define CLK_SPI1		272
#define CLK_SPI2		273
#define CLK_KEYIF		274
#define CLK_I2S1		275
#define CLK_I2S2		276
#define CLK_PCM1		277
#define CLK_PCM2		278
#define CLK_PWM			279
#define CLK_SPDIF		280
#define CLK_USI4		281
#define CLK_USI5		282
#define CLK_USI6		283
#define CLK_ACLK66_PSGEN	300
#define CLK_CHIPID		301
#define CLK_SYSREG		302
#define CLK_TZPC0		303
#define CLK_TZPC1		304
#define CLK_TZPC2		305

Annotation

Implementation Notes