include/dt-bindings/clock/exynos7-clk.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/exynos7-clk.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/exynos7-clk.h
Extension
.h
Size
5131 bytes
Lines
205
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
#define _DT_BINDINGS_CLOCK_EXYNOS7_H

/* TOPC */
#define DOUT_ACLK_PERIS			1
#define DOUT_SCLK_BUS0_PLL		2
#define DOUT_SCLK_BUS1_PLL		3
#define DOUT_SCLK_CC_PLL		4
#define DOUT_SCLK_MFC_PLL		5
#define DOUT_ACLK_CCORE_133		6
#define DOUT_ACLK_MSCL_532		7
#define ACLK_MSCL_532			8
#define DOUT_SCLK_AUD_PLL		9
#define FOUT_AUD_PLL			10
#define SCLK_AUD_PLL			11
#define SCLK_MFC_PLL_B			12
#define SCLK_MFC_PLL_A			13
#define SCLK_BUS1_PLL_B			14
#define SCLK_BUS1_PLL_A			15
#define SCLK_BUS0_PLL_B			16
#define SCLK_BUS0_PLL_A			17
#define SCLK_CC_PLL_B			18
#define SCLK_CC_PLL_A			19
#define ACLK_CCORE_133			20
#define ACLK_PERIS_66			21
#define TOPC_NR_CLK			22

/* TOP0 */
#define DOUT_ACLK_PERIC1		1
#define DOUT_ACLK_PERIC0		2
#define CLK_SCLK_UART0			3
#define CLK_SCLK_UART1			4
#define CLK_SCLK_UART2			5
#define CLK_SCLK_UART3			6
#define CLK_SCLK_SPI0			7
#define CLK_SCLK_SPI1			8
#define CLK_SCLK_SPI2			9
#define CLK_SCLK_SPI3			10
#define CLK_SCLK_SPI4			11
#define CLK_SCLK_SPDIF			12
#define CLK_SCLK_PCM1			13
#define CLK_SCLK_I2S1			14
#define CLK_ACLK_PERIC0_66		15
#define CLK_ACLK_PERIC1_66		16
#define TOP0_NR_CLK			17

/* TOP1 */
#define DOUT_ACLK_FSYS1_200		1
#define DOUT_ACLK_FSYS0_200		2
#define DOUT_SCLK_MMC2			3
#define DOUT_SCLK_MMC1			4
#define DOUT_SCLK_MMC0			5
#define CLK_SCLK_MMC2			6
#define CLK_SCLK_MMC1			7
#define CLK_SCLK_MMC0			8
#define CLK_ACLK_FSYS0_200		9
#define CLK_ACLK_FSYS1_200		10
#define CLK_SCLK_PHY_FSYS1		11
#define CLK_SCLK_PHY_FSYS1_26M		12
#define MOUT_SCLK_UFSUNIPRO20		13
#define DOUT_SCLK_UFSUNIPRO20		14
#define CLK_SCLK_UFSUNIPRO20		15
#define DOUT_SCLK_PHY_FSYS1		16
#define DOUT_SCLK_PHY_FSYS1_26M		17
#define TOP1_NR_CLK			18

/* CCORE */
#define PCLK_RTC			1
#define CCORE_NR_CLK			2

/* PERIC0 */
#define PCLK_UART0			1
#define SCLK_UART0			2
#define PCLK_HSI2C0			3
#define PCLK_HSI2C1			4
#define PCLK_HSI2C4			5
#define PCLK_HSI2C5			6
#define PCLK_HSI2C9			7
#define PCLK_HSI2C10			8
#define PCLK_HSI2C11			9
#define PCLK_PWM			10
#define SCLK_PWM			11
#define PCLK_ADCIF			12
#define PERIC0_NR_CLK			13

/* PERIC1 */
#define PCLK_UART1			1
#define PCLK_UART2			2
#define PCLK_UART3			3
#define SCLK_UART1			4

Annotation

Implementation Notes