include/dt-bindings/clock/exynos7885.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/exynos7885.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/exynos7885.h
Extension
.h
Size
5000 bytes
Lines
158
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLOCK_EXYNOS_7885_H
#define _DT_BINDINGS_CLOCK_EXYNOS_7885_H

/* CMU_TOP */
#define CLK_FOUT_SHARED0_PLL		1
#define CLK_FOUT_SHARED1_PLL		2
#define CLK_DOUT_SHARED0_DIV2		3
#define CLK_DOUT_SHARED0_DIV3		4
#define CLK_DOUT_SHARED0_DIV4		5
#define CLK_DOUT_SHARED0_DIV5		6
#define CLK_DOUT_SHARED1_DIV2		7
#define CLK_DOUT_SHARED1_DIV3		8
#define CLK_DOUT_SHARED1_DIV4		9
#define CLK_MOUT_CORE_BUS		10
#define CLK_MOUT_CORE_CCI		11
#define CLK_MOUT_CORE_G3D		12
#define CLK_DOUT_CORE_BUS		13
#define CLK_DOUT_CORE_CCI		14
#define CLK_DOUT_CORE_G3D		15
#define CLK_GOUT_CORE_BUS		16
#define CLK_GOUT_CORE_CCI		17
#define CLK_GOUT_CORE_G3D		18
#define CLK_MOUT_PERI_BUS		19
#define CLK_MOUT_PERI_SPI0		20
#define CLK_MOUT_PERI_SPI1		21
#define CLK_MOUT_PERI_UART0		22
#define CLK_MOUT_PERI_UART1		23
#define CLK_MOUT_PERI_UART2		24
#define CLK_MOUT_PERI_USI0		25
#define CLK_MOUT_PERI_USI1		26
#define CLK_MOUT_PERI_USI2		27
#define CLK_DOUT_PERI_BUS		28
#define CLK_DOUT_PERI_SPI0		29
#define CLK_DOUT_PERI_SPI1		30
#define CLK_DOUT_PERI_UART0		31
#define CLK_DOUT_PERI_UART1		32
#define CLK_DOUT_PERI_UART2		33
#define CLK_DOUT_PERI_USI0		34
#define CLK_DOUT_PERI_USI1		35
#define CLK_DOUT_PERI_USI2		36
#define CLK_GOUT_PERI_BUS		37
#define CLK_GOUT_PERI_SPI0		38
#define CLK_GOUT_PERI_SPI1		39
#define CLK_GOUT_PERI_UART0		40
#define CLK_GOUT_PERI_UART1		41
#define CLK_GOUT_PERI_UART2		42
#define CLK_GOUT_PERI_USI0		43
#define CLK_GOUT_PERI_USI1		44
#define CLK_GOUT_PERI_USI2		45
#define CLK_MOUT_FSYS_BUS		46
#define CLK_MOUT_FSYS_MMC_CARD		47
#define CLK_MOUT_FSYS_MMC_EMBD		48
#define CLK_MOUT_FSYS_MMC_SDIO		49
#define CLK_MOUT_FSYS_USB30DRD		50
#define CLK_DOUT_FSYS_BUS		51
#define CLK_DOUT_FSYS_MMC_CARD		52
#define CLK_DOUT_FSYS_MMC_EMBD		53
#define CLK_DOUT_FSYS_MMC_SDIO		54
#define CLK_DOUT_FSYS_USB30DRD		55
#define CLK_GOUT_FSYS_BUS		56
#define CLK_GOUT_FSYS_MMC_CARD		57
#define CLK_GOUT_FSYS_MMC_EMBD		58
#define CLK_GOUT_FSYS_MMC_SDIO		59
#define CLK_GOUT_FSYS_USB30DRD		60
#define CLK_MOUT_SHARED0_PLL		61
#define CLK_MOUT_SHARED1_PLL		62

/* CMU_CORE */
#define CLK_MOUT_CORE_BUS_USER			1
#define CLK_MOUT_CORE_CCI_USER			2
#define CLK_MOUT_CORE_G3D_USER			3
#define CLK_MOUT_CORE_GIC			4
#define CLK_DOUT_CORE_BUSP			5
#define CLK_GOUT_CCI_ACLK			6
#define CLK_GOUT_GIC400_CLK			7
#define CLK_GOUT_TREX_D_CORE_ACLK		8
#define CLK_GOUT_TREX_D_CORE_GCLK		9
#define CLK_GOUT_TREX_D_CORE_PCLK		10
#define CLK_GOUT_TREX_P_CORE_ACLK_P_CORE	11
#define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE	12
#define CLK_GOUT_TREX_P_CORE_PCLK		13
#define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE	14

/* CMU_PERI */
#define CLK_MOUT_PERI_BUS_USER		1
#define CLK_MOUT_PERI_SPI0_USER		2
#define CLK_MOUT_PERI_SPI1_USER		3
#define CLK_MOUT_PERI_UART0_USER	4
#define CLK_MOUT_PERI_UART1_USER	5
#define CLK_MOUT_PERI_UART2_USER	6

Annotation

Implementation Notes