include/dt-bindings/clock/fsd-clk.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/fsd-clk.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/fsd-clk.h
Extension
.h
Size
5419 bytes
Lines
157
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLOCK_FSD_H
#define _DT_BINDINGS_CLOCK_FSD_H

/* CMU */
#define DOUT_CMU_PLL_SHARED0_DIV4		1
#define DOUT_CMU_PERIC_SHARED1DIV36		2
#define DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK	3
#define DOUT_CMU_PERIC_SHARED0DIV20		4
#define DOUT_CMU_PERIC_SHARED1DIV4_DMACLK	5
#define DOUT_CMU_PLL_SHARED0_DIV6		6
#define DOUT_CMU_FSYS0_SHARED1DIV4		7
#define DOUT_CMU_FSYS0_SHARED0DIV4		8
#define DOUT_CMU_FSYS1_SHARED0DIV8		9
#define DOUT_CMU_FSYS1_SHARED0DIV4		10
#define CMU_CPUCL_SWITCH_GATE			11
#define DOUT_CMU_IMEM_TCUCLK			12
#define DOUT_CMU_IMEM_ACLK			13
#define DOUT_CMU_IMEM_DMACLK			14
#define GAT_CMU_FSYS0_SHARED0DIV4		15

/* PERIC */
#define PERIC_SCLK_UART0			1
#define PERIC_PCLK_UART0			2
#define PERIC_SCLK_UART1			3
#define PERIC_PCLK_UART1			4
#define PERIC_DMA0_IPCLKPORT_ACLK		5
#define PERIC_DMA1_IPCLKPORT_ACLK		6
#define PERIC_PWM0_IPCLKPORT_I_PCLK_S0		7
#define PERIC_PWM1_IPCLKPORT_I_PCLK_S0		8
#define PERIC_PCLK_SPI0                         9
#define PERIC_SCLK_SPI0                         10
#define PERIC_PCLK_SPI1                         11
#define PERIC_SCLK_SPI1                         12
#define PERIC_PCLK_SPI2                         13
#define PERIC_SCLK_SPI2                         14
#define PERIC_PCLK_TDM0                         15
#define PERIC_PCLK_HSI2C0			16
#define PERIC_PCLK_HSI2C1			17
#define PERIC_PCLK_HSI2C2			18
#define PERIC_PCLK_HSI2C3			19
#define PERIC_PCLK_HSI2C4			20
#define PERIC_PCLK_HSI2C5			21
#define PERIC_PCLK_HSI2C6			22
#define PERIC_PCLK_HSI2C7			23
#define PERIC_MCAN0_IPCLKPORT_CCLK		24
#define PERIC_MCAN0_IPCLKPORT_PCLK		25
#define PERIC_MCAN1_IPCLKPORT_CCLK		26
#define PERIC_MCAN1_IPCLKPORT_PCLK		27
#define PERIC_MCAN2_IPCLKPORT_CCLK		28
#define PERIC_MCAN2_IPCLKPORT_PCLK		29
#define PERIC_MCAN3_IPCLKPORT_CCLK		30
#define PERIC_MCAN3_IPCLKPORT_PCLK		31
#define PERIC_PCLK_ADCIF			32
#define PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I  33
#define PERIC_EQOS_TOP_IPCLKPORT_ACLK_I		34
#define PERIC_EQOS_TOP_IPCLKPORT_HCLK_I		35
#define PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I	36
#define PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I	37
#define PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK	38
#define PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK	39
#define PERIC_HCLK_TDM0				40
#define PERIC_PCLK_TDM1				41
#define PERIC_HCLK_TDM1				42
#define PERIC_EQOS_PHYRXCLK_MUX			43
#define PERIC_EQOS_PHYRXCLK			44
#define PERIC_DOUT_RGMII_CLK			45

/* FSYS0 */
#define UFS0_MPHY_REFCLK_IXTAL24		1
#define UFS0_MPHY_REFCLK_IXTAL26		2
#define UFS1_MPHY_REFCLK_IXTAL24		3
#define UFS1_MPHY_REFCLK_IXTAL26		4
#define UFS0_TOP0_HCLK_BUS			5
#define UFS0_TOP0_ACLK				6
#define UFS0_TOP0_CLK_UNIPRO			7
#define UFS0_TOP0_FMP_CLK			8
#define UFS1_TOP1_HCLK_BUS			9
#define UFS1_TOP1_ACLK				10
#define UFS1_TOP1_CLK_UNIPRO			11
#define UFS1_TOP1_FMP_CLK			12
#define PCIE_SUBCTRL_INST0_DBI_ACLK_SOC		13
#define PCIE_SUBCTRL_INST0_AUX_CLK_SOC		14
#define PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC	15
#define PCIE_SUBCTRL_INST0_SLV_ACLK_SOC		16
#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 17
#define FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I	18
#define FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I	19
#define FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I	20
#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I	21
#define FSYS0_DOUT_FSYS0_PERIBUS_GRP		22

Annotation

Implementation Notes