include/dt-bindings/clock/mediatek,mt6735-infracfg.h

File Facts

System

Linux kernel

Corpus path

include/dt-bindings/clock/mediatek,mt6735-infracfg.h

Extension

.h

Size

672 bytes

Lines

26

Domain

Repository Root And Misc

Bucket

include

Inferred role

Repository Root And Misc: implementation source

Status

source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

• Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef _DT_BINDINGS_CLK_MT6735_INFRACFG_H
#define _DT_BINDINGS_CLK_MT6735_INFRACFG_H

#define CLK_INFRA_DBG			0
#define CLK_INFRA_GCE			1
#define CLK_INFRA_TRBG			2
#define CLK_INFRA_CPUM			3
#define CLK_INFRA_DEVAPC		4
#define CLK_INFRA_AUDIO			5
#define CLK_INFRA_GCPU			6
#define CLK_INFRA_L2C_SRAM		7
#define CLK_INFRA_M4U			8
#define CLK_INFRA_CLDMA			9
#define CLK_INFRA_CONNMCU_BUS		10
#define CLK_INFRA_KP			11
#define CLK_INFRA_APXGPT		12
#define CLK_INFRA_SEJ			13
#define CLK_INFRA_CCIF0_AP		14
#define CLK_INFRA_CCIF1_AP		15
#define CLK_INFRA_PMIC_SPI		16
#define CLK_INFRA_PMIC_WRAP		17

#endif

Annotation

• Atlas domain: Repository Root And Misc / include.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.