include/dt-bindings/clock/mediatek,mt6795-clk.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/mediatek,mt6795-clk.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/mediatek,mt6795-clk.h
Extension
.h
Size
7872 bytes
Lines
276
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLK_MT6795_H
#define _DT_BINDINGS_CLK_MT6795_H

/* TOPCKGEN */
#define CLK_TOP_ADSYS_26M		0
#define CLK_TOP_CLKPH_MCK_O		1
#define CLK_TOP_USB_SYSPLL_125M		2
#define CLK_TOP_DSI0_DIG		3
#define CLK_TOP_DSI1_DIG		4
#define CLK_TOP_ARMCA53PLL_754M		5
#define CLK_TOP_ARMCA53PLL_502M		6
#define CLK_TOP_MAIN_H546M		7
#define CLK_TOP_MAIN_H364M		8
#define CLK_TOP_MAIN_H218P4M		9
#define CLK_TOP_MAIN_H156M		10
#define CLK_TOP_TVDPLL_445P5M		11
#define CLK_TOP_TVDPLL_594M		12
#define CLK_TOP_UNIV_624M		13
#define CLK_TOP_UNIV_416M		14
#define CLK_TOP_UNIV_249P6M		15
#define CLK_TOP_UNIV_178P3M		16
#define CLK_TOP_UNIV_48M		17
#define CLK_TOP_CLKRTC_EXT		18
#define CLK_TOP_CLKRTC_INT		19
#define CLK_TOP_FPC			20
#define CLK_TOP_HDMITXPLL_D2		21
#define CLK_TOP_HDMITXPLL_D3		22
#define CLK_TOP_ARMCA53PLL_D2		23
#define CLK_TOP_ARMCA53PLL_D3		24
#define CLK_TOP_APLL1			25
#define CLK_TOP_APLL2			26
#define CLK_TOP_DMPLL			27
#define CLK_TOP_DMPLL_D2		28
#define CLK_TOP_DMPLL_D4		29
#define CLK_TOP_DMPLL_D8		30
#define CLK_TOP_DMPLL_D16		31
#define CLK_TOP_MMPLL			32
#define CLK_TOP_MMPLL_D2		33
#define CLK_TOP_MSDCPLL			34
#define CLK_TOP_MSDCPLL_D2		35
#define CLK_TOP_MSDCPLL_D4		36
#define CLK_TOP_MSDCPLL2		37
#define CLK_TOP_MSDCPLL2_D2		38
#define CLK_TOP_MSDCPLL2_D4		39
#define CLK_TOP_SYSPLL_D2		40
#define CLK_TOP_SYSPLL1_D2		41
#define CLK_TOP_SYSPLL1_D4		42
#define CLK_TOP_SYSPLL1_D8		43
#define CLK_TOP_SYSPLL1_D16		44
#define CLK_TOP_SYSPLL_D3		45
#define CLK_TOP_SYSPLL2_D2		46
#define CLK_TOP_SYSPLL2_D4		47
#define CLK_TOP_SYSPLL_D5		48
#define CLK_TOP_SYSPLL3_D2		49
#define CLK_TOP_SYSPLL3_D4		50
#define CLK_TOP_SYSPLL_D7		51
#define CLK_TOP_SYSPLL4_D2		52
#define CLK_TOP_SYSPLL4_D4		53
#define CLK_TOP_TVDPLL			54
#define CLK_TOP_TVDPLL_D2		55
#define CLK_TOP_TVDPLL_D4		56
#define CLK_TOP_TVDPLL_D8		57
#define CLK_TOP_TVDPLL_D16		58
#define CLK_TOP_UNIVPLL_D2		59
#define CLK_TOP_UNIVPLL1_D2		60
#define CLK_TOP_UNIVPLL1_D4		61
#define CLK_TOP_UNIVPLL1_D8		62
#define CLK_TOP_UNIVPLL_D3		63
#define CLK_TOP_UNIVPLL2_D2		64
#define CLK_TOP_UNIVPLL2_D4		65
#define CLK_TOP_UNIVPLL2_D8		66
#define CLK_TOP_UNIVPLL_D5		67
#define CLK_TOP_UNIVPLL3_D2		68
#define CLK_TOP_UNIVPLL3_D4		69
#define CLK_TOP_UNIVPLL3_D8		70
#define CLK_TOP_UNIVPLL_D7		71
#define CLK_TOP_UNIVPLL_D26		72
#define CLK_TOP_UNIVPLL_D52		73
#define CLK_TOP_VCODECPLL		74
#define CLK_TOP_VCODECPLL_370P5		75
#define CLK_TOP_VENCPLL			76
#define CLK_TOP_VENCPLL_D2		77
#define CLK_TOP_VENCPLL_D4		78
#define CLK_TOP_AXI_SEL			79
#define CLK_TOP_MEM_SEL			80
#define CLK_TOP_DDRPHYCFG_SEL		81
#define CLK_TOP_MM_SEL			82
#define CLK_TOP_PWM_SEL			83
#define CLK_TOP_VDEC_SEL		84
#define CLK_TOP_VENC_SEL		85

Annotation

Implementation Notes