include/dt-bindings/clock/mediatek,mt7988-clk.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/mediatek,mt7988-clk.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/mediatek,mt7988-clk.h
Extension
.h
Size
8703 bytes
Lines
281
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLK_MT7988_H
#define _DT_BINDINGS_CLK_MT7988_H

/* APMIXEDSYS */

#define CLK_APMIXED_NETSYSPLL			0
#define CLK_APMIXED_MPLL			1
#define CLK_APMIXED_MMPLL			2
#define CLK_APMIXED_APLL2			3
#define CLK_APMIXED_NET1PLL			4
#define CLK_APMIXED_NET2PLL			5
#define CLK_APMIXED_WEDMCUPLL			6
#define CLK_APMIXED_SGMPLL			7
#define CLK_APMIXED_ARM_B			8
#define CLK_APMIXED_CCIPLL2_B			9
#define CLK_APMIXED_USXGMIIPLL			10
#define CLK_APMIXED_MSDCPLL			11

/* TOPCKGEN */

#define CLK_TOP_XTAL				0
#define CLK_TOP_XTAL_D2				1
#define CLK_TOP_RTC_32K				2
#define CLK_TOP_RTC_32P7K			3
#define CLK_TOP_MPLL_D2				4
#define CLK_TOP_MPLL_D3_D2			5
#define CLK_TOP_MPLL_D4				6
#define CLK_TOP_MPLL_D8				7
#define CLK_TOP_MPLL_D8_D2			8
#define CLK_TOP_MMPLL_D2			9
#define CLK_TOP_MMPLL_D3_D5			10
#define CLK_TOP_MMPLL_D4			11
#define CLK_TOP_MMPLL_D6_D2			12
#define CLK_TOP_MMPLL_D8			13
#define CLK_TOP_APLL2_D4			14
#define CLK_TOP_NET1PLL_D4			15
#define CLK_TOP_NET1PLL_D5			16
#define CLK_TOP_NET1PLL_D5_D2			17
#define CLK_TOP_NET1PLL_D5_D4			18
#define CLK_TOP_NET1PLL_D8			19
#define CLK_TOP_NET1PLL_D8_D2			20
#define CLK_TOP_NET1PLL_D8_D4			21
#define CLK_TOP_NET1PLL_D8_D8			22
#define CLK_TOP_NET1PLL_D8_D16			23
#define CLK_TOP_NET2PLL_D2			24
#define CLK_TOP_NET2PLL_D4			25
#define CLK_TOP_NET2PLL_D4_D4			26
#define CLK_TOP_NET2PLL_D4_D8			27
#define CLK_TOP_NET2PLL_D6			28
#define CLK_TOP_NET2PLL_D8			29
#define CLK_TOP_NETSYS_SEL			30
#define CLK_TOP_NETSYS_500M_SEL			31
#define CLK_TOP_NETSYS_2X_SEL			32
#define CLK_TOP_NETSYS_GSW_SEL			33
#define CLK_TOP_ETH_GMII_SEL			34
#define CLK_TOP_NETSYS_MCU_SEL			35
#define CLK_TOP_NETSYS_PAO_2X_SEL		36
#define CLK_TOP_EIP197_SEL			37
#define CLK_TOP_AXI_INFRA_SEL			38
#define CLK_TOP_UART_SEL			39
#define CLK_TOP_EMMC_250M_SEL			40
#define CLK_TOP_EMMC_400M_SEL			41
#define CLK_TOP_SPI_SEL				42
#define CLK_TOP_SPIM_MST_SEL			43
#define CLK_TOP_NFI1X_SEL			44
#define CLK_TOP_SPINFI_SEL			45
#define CLK_TOP_PWM_SEL				46
#define CLK_TOP_I2C_SEL				47
#define CLK_TOP_PCIE_MBIST_250M_SEL		48
#define CLK_TOP_PEXTP_TL_SEL			49
#define CLK_TOP_PEXTP_TL_P1_SEL			50
#define CLK_TOP_PEXTP_TL_P2_SEL			51
#define CLK_TOP_PEXTP_TL_P3_SEL			52
#define CLK_TOP_USB_SYS_SEL			53
#define CLK_TOP_USB_SYS_P1_SEL			54
#define CLK_TOP_USB_XHCI_SEL			55
#define CLK_TOP_USB_XHCI_P1_SEL			56
#define CLK_TOP_USB_FRMCNT_SEL			57
#define CLK_TOP_USB_FRMCNT_P1_SEL		58
#define CLK_TOP_AUD_SEL				59
#define CLK_TOP_A1SYS_SEL			60
#define CLK_TOP_AUD_L_SEL			61
#define CLK_TOP_A_TUNER_SEL			62
#define CLK_TOP_SSPXTP_SEL			63
#define CLK_TOP_USB_PHY_SEL			64
#define CLK_TOP_USXGMII_SBUS_0_SEL		65
#define CLK_TOP_USXGMII_SBUS_1_SEL		66
#define CLK_TOP_SGM_0_SEL			67
#define CLK_TOP_SGM_SBUS_0_SEL			68
#define CLK_TOP_SGM_1_SEL			69

Annotation

Implementation Notes