include/dt-bindings/clock/mediatek,mt8188-clk.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/mediatek,mt8188-clk.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/mediatek,mt8188-clk.h
Extension
.h
Size
22611 bytes
Lines
727
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLK_MT8188_H
#define _DT_BINDINGS_CLK_MT8188_H

/* TOPCKGEN */
#define CLK_TOP_AXI				0
#define CLK_TOP_SPM				1
#define CLK_TOP_SCP				2
#define CLK_TOP_BUS_AXIMEM			3
#define CLK_TOP_VPP				4
#define CLK_TOP_ETHDR				5
#define CLK_TOP_IPE				6
#define CLK_TOP_CAM				7
#define CLK_TOP_CCU				8
#define CLK_TOP_CCU_AHB				9
#define CLK_TOP_IMG				10
#define CLK_TOP_CAMTM				11
#define CLK_TOP_DSP				12
#define CLK_TOP_DSP1				13
#define CLK_TOP_DSP2				14
#define CLK_TOP_DSP3				15
#define CLK_TOP_DSP4				16
#define CLK_TOP_DSP5				17
#define CLK_TOP_DSP6				18
#define CLK_TOP_DSP7				19
#define CLK_TOP_MFG_CORE_TMP			20
#define CLK_TOP_CAMTG				21
#define CLK_TOP_CAMTG2				22
#define CLK_TOP_CAMTG3				23
#define CLK_TOP_UART				24
#define CLK_TOP_SPI				25
#define CLK_TOP_MSDC50_0_HCLK			26
#define CLK_TOP_MSDC50_0			27
#define CLK_TOP_MSDC30_1			28
#define CLK_TOP_MSDC30_2			29
#define CLK_TOP_INTDIR				30
#define CLK_TOP_AUD_INTBUS			31
#define CLK_TOP_AUDIO_H				32
#define CLK_TOP_PWRAP_ULPOSC			33
#define CLK_TOP_ATB				34
#define CLK_TOP_SSPM				35
#define CLK_TOP_DP				36
#define CLK_TOP_EDP				37
#define CLK_TOP_DPI				38
#define CLK_TOP_DISP_PWM0			39
#define CLK_TOP_DISP_PWM1			40
#define CLK_TOP_USB_TOP				41
#define CLK_TOP_SSUSB_XHCI			42
#define CLK_TOP_USB_TOP_2P			43
#define CLK_TOP_SSUSB_XHCI_2P			44
#define CLK_TOP_USB_TOP_3P			45
#define CLK_TOP_SSUSB_XHCI_3P			46
#define CLK_TOP_I2C				47
#define CLK_TOP_SENINF				48
#define CLK_TOP_SENINF1				49
#define CLK_TOP_GCPU				50
#define CLK_TOP_VENC				51
#define CLK_TOP_VDEC				52
#define CLK_TOP_PWM				53
#define CLK_TOP_MCUPM				54
#define CLK_TOP_SPMI_P_MST			55
#define CLK_TOP_SPMI_M_MST			56
#define CLK_TOP_DVFSRC				57
#define CLK_TOP_TL				58
#define CLK_TOP_AES_MSDCFDE			59
#define CLK_TOP_DSI_OCC				60
#define CLK_TOP_WPE_VPP				61
#define CLK_TOP_HDCP				62
#define CLK_TOP_HDCP_24M			63
#define CLK_TOP_HDMI_APB			64
#define CLK_TOP_SNPS_ETH_250M			65
#define CLK_TOP_SNPS_ETH_62P4M_PTP		66
#define CLK_TOP_SNPS_ETH_50M_RMII		67
#define CLK_TOP_ADSP				68
#define CLK_TOP_AUDIO_LOCAL_BUS			69
#define CLK_TOP_ASM_H				70
#define CLK_TOP_ASM_L				71
#define CLK_TOP_APLL1				72
#define CLK_TOP_APLL2				73
#define CLK_TOP_APLL3				74
#define CLK_TOP_APLL4				75
#define CLK_TOP_APLL5				76
#define CLK_TOP_I2SO1				77
#define CLK_TOP_I2SO2				78
#define CLK_TOP_I2SI1				79
#define CLK_TOP_I2SI2				80
#define CLK_TOP_DPTX				81
#define CLK_TOP_AUD_IEC				82
#define CLK_TOP_A1SYS_HP			83
#define CLK_TOP_A2SYS				84
#define CLK_TOP_A3SYS				85

Annotation

Implementation Notes