include/dt-bindings/clock/mediatek,mt8196-clock.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/mediatek,mt8196-clock.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/mediatek,mt8196-clock.h
Extension
.h
Size
25170 bytes
Lines
804
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLK_MT8196_H
#define _DT_BINDINGS_CLK_MT8196_H

/* CKSYS */
#define CLK_TOP_AXI					0
#define CLK_TOP_MEM_SUB					1
#define CLK_TOP_IO_NOC					2
#define CLK_TOP_P_AXI					3
#define CLK_TOP_UFS_PEXTP0_AXI				4
#define CLK_TOP_PEXTP1_USB_AXI				5
#define CLK_TOP_P_FMEM_SUB				6
#define CLK_TOP_PEXPT0_MEM_SUB				7
#define CLK_TOP_PEXTP1_USB_MEM_SUB			8
#define CLK_TOP_P_NOC					9
#define CLK_TOP_EMI_N					10
#define CLK_TOP_EMI_S					11
#define CLK_TOP_AP2CONN_HOST				12
#define CLK_TOP_ATB					13
#define CLK_TOP_CIRQ					14
#define CLK_TOP_PBUS_156M				15
#define CLK_TOP_EFUSE					16
#define CLK_TOP_MCL3GIC					17
#define CLK_TOP_MCINFRA					18
#define CLK_TOP_DSP					19
#define CLK_TOP_MFG_REF					20
#define CLK_TOP_MFG_EB					21
#define CLK_TOP_UART					22
#define CLK_TOP_SPI0_BCLK				23
#define CLK_TOP_SPI1_BCLK				24
#define CLK_TOP_SPI2_BCLK				25
#define CLK_TOP_SPI3_BCLK				26
#define CLK_TOP_SPI4_BCLK				27
#define CLK_TOP_SPI5_BCLK				28
#define CLK_TOP_SPI6_BCLK				29
#define CLK_TOP_SPI7_BCLK				30
#define CLK_TOP_MSDC30_1				31
#define CLK_TOP_MSDC30_2				32
#define CLK_TOP_DISP_PWM				33
#define CLK_TOP_USB_TOP_1P				34
#define CLK_TOP_USB_XHCI_1P				35
#define CLK_TOP_USB_FMCNT_P1				36
#define CLK_TOP_I2C_P					37
#define CLK_TOP_I2C_EAST				38
#define CLK_TOP_I2C_WEST				39
#define CLK_TOP_I2C_NORTH				40
#define CLK_TOP_AES_UFSFDE				41
#define CLK_TOP_UFS					42
#define CLK_TOP_AUD_1					43
#define CLK_TOP_AUD_2					44
#define CLK_TOP_ADSP					45
#define CLK_TOP_ADSP_UARTHUB_B				46
#define CLK_TOP_DPMAIF_MAIN				47
#define CLK_TOP_PWM					48
#define CLK_TOP_MCUPM					49
#define CLK_TOP_IPSEAST					50
#define CLK_TOP_TL					51
#define CLK_TOP_TL_P1					52
#define CLK_TOP_TL_P2					53
#define CLK_TOP_EMI_INTERFACE_546			54
#define CLK_TOP_SDF					55
#define CLK_TOP_UARTHUB_BCLK				56
#define CLK_TOP_DPSW_CMP_26M				57
#define CLK_TOP_SMAP					58
#define CLK_TOP_SSR_PKA					59
#define CLK_TOP_SSR_DMA					60
#define CLK_TOP_SSR_KDF					61
#define CLK_TOP_SSR_RNG					62
#define CLK_TOP_SPU0					63
#define CLK_TOP_SPU1					64
#define CLK_TOP_DXCC					65
#define CLK_TOP_APLL_I2SIN0				66
#define CLK_TOP_APLL_I2SIN1				67
#define CLK_TOP_APLL_I2SIN2				68
#define CLK_TOP_APLL_I2SIN3				69
#define CLK_TOP_APLL_I2SIN4				70
#define CLK_TOP_APLL_I2SIN6				71
#define CLK_TOP_APLL_I2SOUT0				72
#define CLK_TOP_APLL_I2SOUT1				73
#define CLK_TOP_APLL_I2SOUT2				74
#define CLK_TOP_APLL_I2SOUT3				75
#define CLK_TOP_APLL_I2SOUT4				76
#define CLK_TOP_APLL_I2SOUT6				77
#define CLK_TOP_APLL_FMI2S				78
#define CLK_TOP_APLL_TDMOUT				79
#define CLK_TOP_APLL12_DIV_TDMOUT_M			80
#define CLK_TOP_APLL12_DIV_TDMOUT_B			81
#define CLK_TOP_MAINPLL_D3				82
#define CLK_TOP_MAINPLL_D4				83
#define CLK_TOP_MAINPLL_D4_D2				84
#define CLK_TOP_MAINPLL_D4_D4				85

Annotation

Implementation Notes