include/dt-bindings/clock/mediatek,mt8365-clk.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/mediatek,mt8365-clk.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/mediatek,mt8365-clk.h
Extension
.h
Size
10381 bytes
Lines
374
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLK_MT8365_H
#define _DT_BINDINGS_CLK_MT8365_H

/* TOPCKGEN */
#define CLK_TOP_CLK_NULL		0
#define CLK_TOP_I2S0_BCK		1
#define CLK_TOP_DSI0_LNTC_DSICK		2
#define CLK_TOP_VPLL_DPIX		3
#define CLK_TOP_LVDSTX_CLKDIG_CTS	4
#define CLK_TOP_MFGPLL			5
#define CLK_TOP_SYSPLL_D2		6
#define CLK_TOP_SYSPLL1_D2		7
#define CLK_TOP_SYSPLL1_D4		8
#define CLK_TOP_SYSPLL1_D8		9
#define CLK_TOP_SYSPLL1_D16		10
#define CLK_TOP_SYSPLL_D3		11
#define CLK_TOP_SYSPLL2_D2		12
#define CLK_TOP_SYSPLL2_D4		13
#define CLK_TOP_SYSPLL2_D8		14
#define CLK_TOP_SYSPLL_D5		15
#define CLK_TOP_SYSPLL3_D2		16
#define CLK_TOP_SYSPLL3_D4		17
#define CLK_TOP_SYSPLL_D7		18
#define CLK_TOP_SYSPLL4_D2		19
#define CLK_TOP_SYSPLL4_D4		20
#define CLK_TOP_UNIVPLL			21
#define CLK_TOP_UNIVPLL_D2		22
#define CLK_TOP_UNIVPLL1_D2		23
#define CLK_TOP_UNIVPLL1_D4		24
#define CLK_TOP_UNIVPLL_D3		25
#define CLK_TOP_UNIVPLL2_D2		26
#define CLK_TOP_UNIVPLL2_D4		27
#define CLK_TOP_UNIVPLL2_D8		28
#define CLK_TOP_UNIVPLL2_D32		29
#define CLK_TOP_UNIVPLL_D5		30
#define CLK_TOP_UNIVPLL3_D2		31
#define CLK_TOP_UNIVPLL3_D4		32
#define CLK_TOP_MMPLL			33
#define CLK_TOP_MMPLL_D2		34
#define CLK_TOP_LVDSPLL_D2		35
#define CLK_TOP_LVDSPLL_D4		36
#define CLK_TOP_LVDSPLL_D8		37
#define CLK_TOP_LVDSPLL_D16		38
#define CLK_TOP_USB20_192M		39
#define CLK_TOP_USB20_192M_D4		40
#define CLK_TOP_USB20_192M_D8		41
#define CLK_TOP_USB20_192M_D16		42
#define CLK_TOP_USB20_192M_D32		43
#define CLK_TOP_APLL1			44
#define CLK_TOP_APLL1_D2		45
#define CLK_TOP_APLL1_D4		46
#define CLK_TOP_APLL1_D8		47
#define CLK_TOP_APLL2			48
#define CLK_TOP_APLL2_D2		49
#define CLK_TOP_APLL2_D4		50
#define CLK_TOP_APLL2_D8		51
#define CLK_TOP_SYS_26M_D2		52
#define CLK_TOP_MSDCPLL			53
#define CLK_TOP_MSDCPLL_D2		54
#define CLK_TOP_DSPPLL			55
#define CLK_TOP_DSPPLL_D2		56
#define CLK_TOP_DSPPLL_D4		57
#define CLK_TOP_DSPPLL_D8		58
#define CLK_TOP_APUPLL			59
#define CLK_TOP_CLK26M_D52		60
#define CLK_TOP_AXI_SEL			61
#define CLK_TOP_MEM_SEL			62
#define CLK_TOP_MM_SEL			63
#define CLK_TOP_SCP_SEL			64
#define CLK_TOP_MFG_SEL			65
#define CLK_TOP_ATB_SEL			66
#define CLK_TOP_CAMTG_SEL		67
#define CLK_TOP_CAMTG1_SEL		68
#define CLK_TOP_UART_SEL		69
#define CLK_TOP_SPI_SEL			70
#define CLK_TOP_MSDC50_0_HC_SEL		71
#define CLK_TOP_MSDC2_2_HC_SEL		72
#define CLK_TOP_MSDC50_0_SEL		73
#define CLK_TOP_MSDC50_2_SEL		74
#define CLK_TOP_MSDC30_1_SEL		75
#define CLK_TOP_AUDIO_SEL		76
#define CLK_TOP_AUD_INTBUS_SEL		77
#define CLK_TOP_AUD_1_SEL		78
#define CLK_TOP_AUD_2_SEL		79
#define CLK_TOP_AUD_ENGEN1_SEL		80
#define CLK_TOP_AUD_ENGEN2_SEL		81
#define CLK_TOP_AUD_SPDIF_SEL		82
#define CLK_TOP_DISP_PWM_SEL		83
#define CLK_TOP_DXCC_SEL		84
#define CLK_TOP_SSUSB_SYS_SEL		85

Annotation

Implementation Notes