include/dt-bindings/clock/mediatek,mtmips-sysc.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/mediatek,mtmips-sysc.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/mediatek,mtmips-sysc.h
Extension
.h
Size
3211 bytes
Lines
131
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLK_MTMIPS_H
#define _DT_BINDINGS_CLK_MTMIPS_H

/* Ralink RT-2880 clocks */

#define RT2880_CLK_XTAL		0
#define RT2880_CLK_CPU		1
#define RT2880_CLK_BUS		2
#define RT2880_CLK_TIMER	3
#define RT2880_CLK_WATCHDOG	4
#define RT2880_CLK_UART		5
#define RT2880_CLK_I2C		6
#define RT2880_CLK_UARTLITE	7
#define RT2880_CLK_ETHERNET	8
#define RT2880_CLK_WMAC		9

/* Ralink RT-305X clocks */

#define RT305X_CLK_XTAL		0
#define RT305X_CLK_CPU		1
#define RT305X_CLK_BUS		2
#define RT305X_CLK_TIMER	3
#define RT305X_CLK_WATCHDOG	4
#define RT305X_CLK_UART		5
#define RT305X_CLK_I2C		6
#define RT305X_CLK_I2S		7
#define RT305X_CLK_SPI1		8
#define RT305X_CLK_SPI2		9
#define RT305X_CLK_UARTLITE	10
#define RT305X_CLK_ETHERNET	11
#define RT305X_CLK_WMAC		12

/* Ralink RT-3352 clocks */

#define RT3352_CLK_XTAL		0
#define RT3352_CLK_CPU		1
#define RT3352_CLK_PERIPH	2
#define RT3352_CLK_BUS		3
#define RT3352_CLK_TIMER	4
#define RT3352_CLK_WATCHDOG	5
#define RT3352_CLK_UART		6
#define RT3352_CLK_I2C		7
#define RT3352_CLK_I2S		8
#define RT3352_CLK_SPI1		9
#define RT3352_CLK_SPI2		10
#define RT3352_CLK_UARTLITE	11
#define RT3352_CLK_ETHERNET	12
#define RT3352_CLK_WMAC		13

/* Ralink RT-3883 clocks */

#define RT3883_CLK_XTAL		0
#define RT3883_CLK_CPU		1
#define RT3883_CLK_BUS		2
#define RT3883_CLK_PERIPH	3
#define RT3883_CLK_TIMER	4
#define RT3883_CLK_WATCHDOG	5
#define RT3883_CLK_UART		6
#define RT3883_CLK_I2C		7
#define RT3883_CLK_I2S		8
#define RT3883_CLK_SPI1		9
#define RT3883_CLK_SPI2		10
#define RT3883_CLK_UARTLITE	11
#define RT3883_CLK_ETHERNET	12
#define RT3883_CLK_WMAC		13

/* Ralink RT-5350 clocks */

#define RT5350_CLK_XTAL		0
#define RT5350_CLK_CPU		1
#define RT5350_CLK_BUS		2
#define RT5350_CLK_PERIPH	3
#define RT5350_CLK_TIMER	4
#define RT5350_CLK_WATCHDOG	5
#define RT5350_CLK_UART		6
#define RT5350_CLK_I2C		7
#define RT5350_CLK_I2S		8
#define RT5350_CLK_SPI1		9
#define RT5350_CLK_SPI2		10
#define RT5350_CLK_UARTLITE	11
#define RT5350_CLK_ETHERNET	12
#define RT5350_CLK_WMAC		13

/* Ralink MT-7620 clocks */

#define MT7620_CLK_XTAL		0
#define MT7620_CLK_PLL		1
#define MT7620_CLK_CPU		2
#define MT7620_CLK_PERIPH	3
#define MT7620_CLK_BUS		4

Annotation

Implementation Notes