include/dt-bindings/clock/mt2701-clk.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/mt2701-clk.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/mt2701-clk.h
Extension
.h
Size
13585 bytes
Lines
485
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLK_MT2701_H
#define _DT_BINDINGS_CLK_MT2701_H

/* TOPCKGEN */
#define CLK_TOP_SYSPLL				1
#define CLK_TOP_SYSPLL_D2			2
#define CLK_TOP_SYSPLL_D3			3
#define CLK_TOP_SYSPLL_D5			4
#define CLK_TOP_SYSPLL_D7			5
#define CLK_TOP_SYSPLL1_D2			6
#define CLK_TOP_SYSPLL1_D4			7
#define CLK_TOP_SYSPLL1_D8			8
#define CLK_TOP_SYSPLL1_D16			9
#define CLK_TOP_SYSPLL2_D2			10
#define CLK_TOP_SYSPLL2_D4			11
#define CLK_TOP_SYSPLL2_D8			12
#define CLK_TOP_SYSPLL3_D2			13
#define CLK_TOP_SYSPLL3_D4			14
#define CLK_TOP_SYSPLL4_D2			15
#define CLK_TOP_SYSPLL4_D4			16
#define CLK_TOP_UNIVPLL				17
#define CLK_TOP_UNIVPLL_D2			18
#define CLK_TOP_UNIVPLL_D3			19
#define CLK_TOP_UNIVPLL_D5			20
#define CLK_TOP_UNIVPLL_D7			21
#define CLK_TOP_UNIVPLL_D26			22
#define CLK_TOP_UNIVPLL_D52			23
#define CLK_TOP_UNIVPLL_D108			24
#define CLK_TOP_USB_PHY48M			25
#define CLK_TOP_UNIVPLL1_D2			26
#define CLK_TOP_UNIVPLL1_D4			27
#define CLK_TOP_UNIVPLL1_D8			28
#define CLK_TOP_UNIVPLL2_D2			29
#define CLK_TOP_UNIVPLL2_D4			30
#define CLK_TOP_UNIVPLL2_D8			31
#define CLK_TOP_UNIVPLL2_D16			32
#define CLK_TOP_UNIVPLL2_D32			33
#define CLK_TOP_UNIVPLL3_D2			34
#define CLK_TOP_UNIVPLL3_D4			35
#define CLK_TOP_UNIVPLL3_D8			36
#define CLK_TOP_MSDCPLL				37
#define CLK_TOP_MSDCPLL_D2			38
#define CLK_TOP_MSDCPLL_D4			39
#define CLK_TOP_MSDCPLL_D8			40
#define CLK_TOP_MMPLL				41
#define CLK_TOP_MMPLL_D2			42
#define CLK_TOP_DMPLL				43
#define CLK_TOP_DMPLL_D2			44
#define CLK_TOP_DMPLL_D4			45
#define CLK_TOP_DMPLL_X2			46
#define CLK_TOP_TVDPLL				47
#define CLK_TOP_TVDPLL_D2			48
#define CLK_TOP_TVDPLL_D4			49
#define CLK_TOP_TVD2PLL				50
#define CLK_TOP_TVD2PLL_D2			51
#define CLK_TOP_HADDS2PLL_98M			52
#define CLK_TOP_HADDS2PLL_294M			53
#define CLK_TOP_HADDS2_FB			54
#define CLK_TOP_MIPIPLL_D2			55
#define CLK_TOP_MIPIPLL_D4			56
#define CLK_TOP_HDMIPLL				57
#define CLK_TOP_HDMIPLL_D2			58
#define CLK_TOP_HDMIPLL_D3			59
#define CLK_TOP_HDMI_SCL_RX			60
#define CLK_TOP_HDMI_0_PIX340M			61
#define CLK_TOP_HDMI_0_DEEP340M			62
#define CLK_TOP_HDMI_0_PLL340M			63
#define CLK_TOP_AUD1PLL_98M			64
#define CLK_TOP_AUD2PLL_90M			65
#define CLK_TOP_AUDPLL				66
#define CLK_TOP_AUDPLL_D4			67
#define CLK_TOP_AUDPLL_D8			68
#define CLK_TOP_AUDPLL_D16			69
#define CLK_TOP_AUDPLL_D24			70
#define CLK_TOP_ETHPLL_500M			71
#define CLK_TOP_VDECPLL				72
#define CLK_TOP_VENCPLL				73
#define CLK_TOP_MIPIPLL				74
#define CLK_TOP_ARMPLL_1P3G			75

#define CLK_TOP_MM_SEL				76
#define CLK_TOP_DDRPHYCFG_SEL			77
#define CLK_TOP_MEM_SEL				78
#define CLK_TOP_AXI_SEL				79
#define CLK_TOP_CAMTG_SEL			80
#define CLK_TOP_MFG_SEL				81
#define CLK_TOP_VDEC_SEL			82
#define CLK_TOP_PWM_SEL				83
#define CLK_TOP_MSDC30_0_SEL			84
#define CLK_TOP_USB20_SEL			85

Annotation

Implementation Notes