include/dt-bindings/clock/mt6779-clk.h
Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/mt6779-clk.h
File Facts
- System
- Linux kernel
- Corpus path
include/dt-bindings/clock/mt6779-clk.h- Extension
.h- Size
- 12540 bytes
- Lines
- 437
- Domain
- Repository Root And Misc
- Bucket
- include
- Inferred role
- Repository Root And Misc: implementation source
- Status
- source implementation candidate
Why This File Exists
Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
- Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _DT_BINDINGS_CLK_MT6779_H
#define _DT_BINDINGS_CLK_MT6779_H
/* TOPCKGEN */
#define CLK_TOP_AXI 1
#define CLK_TOP_MM 2
#define CLK_TOP_CAM 3
#define CLK_TOP_MFG 4
#define CLK_TOP_CAMTG 5
#define CLK_TOP_UART 6
#define CLK_TOP_SPI 7
#define CLK_TOP_MSDC50_0_HCLK 8
#define CLK_TOP_MSDC50_0 9
#define CLK_TOP_MSDC30_1 10
#define CLK_TOP_MSDC30_2 11
#define CLK_TOP_AUD 12
#define CLK_TOP_AUD_INTBUS 13
#define CLK_TOP_FPWRAP_ULPOSC 14
#define CLK_TOP_SCP 15
#define CLK_TOP_ATB 16
#define CLK_TOP_SSPM 17
#define CLK_TOP_DPI0 18
#define CLK_TOP_SCAM 19
#define CLK_TOP_AUD_1 20
#define CLK_TOP_AUD_2 21
#define CLK_TOP_DISP_PWM 22
#define CLK_TOP_SSUSB_TOP_XHCI 23
#define CLK_TOP_USB_TOP 24
#define CLK_TOP_SPM 25
#define CLK_TOP_I2C 26
#define CLK_TOP_F52M_MFG 27
#define CLK_TOP_SENINF 28
#define CLK_TOP_DXCC 29
#define CLK_TOP_CAMTG2 30
#define CLK_TOP_AUD_ENG1 31
#define CLK_TOP_AUD_ENG2 32
#define CLK_TOP_FAES_UFSFDE 33
#define CLK_TOP_FUFS 34
#define CLK_TOP_IMG 35
#define CLK_TOP_DSP 36
#define CLK_TOP_DSP1 37
#define CLK_TOP_DSP2 38
#define CLK_TOP_IPU_IF 39
#define CLK_TOP_CAMTG3 40
#define CLK_TOP_CAMTG4 41
#define CLK_TOP_PMICSPI 42
#define CLK_TOP_MAINPLL_CK 43
#define CLK_TOP_MAINPLL_D2 44
#define CLK_TOP_MAINPLL_D3 45
#define CLK_TOP_MAINPLL_D5 46
#define CLK_TOP_MAINPLL_D7 47
#define CLK_TOP_MAINPLL_D2_D2 48
#define CLK_TOP_MAINPLL_D2_D4 49
#define CLK_TOP_MAINPLL_D2_D8 50
#define CLK_TOP_MAINPLL_D2_D16 51
#define CLK_TOP_MAINPLL_D3_D2 52
#define CLK_TOP_MAINPLL_D3_D4 53
#define CLK_TOP_MAINPLL_D3_D8 54
#define CLK_TOP_MAINPLL_D5_D2 55
#define CLK_TOP_MAINPLL_D5_D4 56
#define CLK_TOP_MAINPLL_D7_D2 57
#define CLK_TOP_MAINPLL_D7_D4 58
#define CLK_TOP_UNIVPLL_CK 59
#define CLK_TOP_UNIVPLL_D2 60
#define CLK_TOP_UNIVPLL_D3 61
#define CLK_TOP_UNIVPLL_D5 62
#define CLK_TOP_UNIVPLL_D7 63
#define CLK_TOP_UNIVPLL_D2_D2 64
#define CLK_TOP_UNIVPLL_D2_D4 65
#define CLK_TOP_UNIVPLL_D2_D8 66
#define CLK_TOP_UNIVPLL_D3_D2 67
#define CLK_TOP_UNIVPLL_D3_D4 68
#define CLK_TOP_UNIVPLL_D3_D8 69
#define CLK_TOP_UNIVPLL_D5_D2 70
#define CLK_TOP_UNIVPLL_D5_D4 71
#define CLK_TOP_UNIVPLL_D5_D8 72
#define CLK_TOP_APLL1_CK 73
#define CLK_TOP_APLL1_D2 74
#define CLK_TOP_APLL1_D4 75
#define CLK_TOP_APLL1_D8 76
#define CLK_TOP_APLL2_CK 77
#define CLK_TOP_APLL2_D2 78
#define CLK_TOP_APLL2_D4 79
#define CLK_TOP_APLL2_D8 80
#define CLK_TOP_TVDPLL_CK 81
#define CLK_TOP_TVDPLL_D2 82
#define CLK_TOP_TVDPLL_D4 83
#define CLK_TOP_TVDPLL_D8 84
#define CLK_TOP_TVDPLL_D16 85
#define CLK_TOP_MSDCPLL_CK 86
Annotation
- Atlas domain: Repository Root And Misc / include.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.