include/dt-bindings/clock/mt7986-clk.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/mt7986-clk.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/mt7986-clk.h
Extension
.h
Size
4782 bytes
Lines
170
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLK_MT7986_H
#define _DT_BINDINGS_CLK_MT7986_H

/* APMIXEDSYS */

#define CLK_APMIXED_ARMPLL		0
#define CLK_APMIXED_NET2PLL		1
#define CLK_APMIXED_MMPLL		2
#define CLK_APMIXED_SGMPLL		3
#define CLK_APMIXED_WEDMCUPLL		4
#define CLK_APMIXED_NET1PLL		5
#define CLK_APMIXED_MPLL		6
#define CLK_APMIXED_APLL2		7

/* TOPCKGEN */

#define CLK_TOP_XTAL			0
#define CLK_TOP_XTAL_D2			1
#define CLK_TOP_RTC_32K			2
#define CLK_TOP_RTC_32P7K		3
#define CLK_TOP_MPLL_D2			4
#define CLK_TOP_MPLL_D4			5
#define CLK_TOP_MPLL_D8			6
#define CLK_TOP_MPLL_D8_D2		7
#define CLK_TOP_MPLL_D3_D2		8
#define CLK_TOP_MMPLL_D2		9
#define CLK_TOP_MMPLL_D4		10
#define CLK_TOP_MMPLL_D8		11
#define CLK_TOP_MMPLL_D8_D2		12
#define CLK_TOP_MMPLL_D3_D8		13
#define CLK_TOP_MMPLL_U2PHY		14
#define CLK_TOP_APLL2_D4		15
#define CLK_TOP_NET1PLL_D4		16
#define CLK_TOP_NET1PLL_D5		17
#define CLK_TOP_NET1PLL_D5_D2		18
#define CLK_TOP_NET1PLL_D5_D4		19
#define CLK_TOP_NET1PLL_D8_D2		20
#define CLK_TOP_NET1PLL_D8_D4		21
#define CLK_TOP_NET2PLL_D4		22
#define CLK_TOP_NET2PLL_D4_D2		23
#define CLK_TOP_NET2PLL_D3_D2		24
#define CLK_TOP_WEDMCUPLL_D5_D2		25
#define CLK_TOP_NFI1X_SEL		26
#define CLK_TOP_SPINFI_SEL		27
#define CLK_TOP_SPI_SEL			28
#define CLK_TOP_SPIM_MST_SEL		29
#define CLK_TOP_UART_SEL		30
#define CLK_TOP_PWM_SEL			31
#define CLK_TOP_I2C_SEL			32
#define CLK_TOP_PEXTP_TL_SEL		33
#define CLK_TOP_EMMC_250M_SEL		34
#define CLK_TOP_EMMC_416M_SEL		35
#define CLK_TOP_F_26M_ADC_SEL		36
#define CLK_TOP_DRAMC_SEL		37
#define CLK_TOP_DRAMC_MD32_SEL		38
#define CLK_TOP_SYSAXI_SEL		39
#define CLK_TOP_SYSAPB_SEL		40
#define CLK_TOP_ARM_DB_MAIN_SEL		41
#define CLK_TOP_ARM_DB_JTSEL		42
#define CLK_TOP_NETSYS_SEL		43
#define CLK_TOP_NETSYS_500M_SEL		44
#define CLK_TOP_NETSYS_MCU_SEL		45
#define CLK_TOP_NETSYS_2X_SEL		46
#define CLK_TOP_SGM_325M_SEL		47
#define CLK_TOP_SGM_REG_SEL		48
#define CLK_TOP_A1SYS_SEL		49
#define CLK_TOP_CONN_MCUSYS_SEL		50
#define CLK_TOP_EIP_B_SEL		51
#define CLK_TOP_PCIE_PHY_SEL		52
#define CLK_TOP_USB3_PHY_SEL		53
#define CLK_TOP_F26M_SEL		54
#define CLK_TOP_AUD_L_SEL		55
#define CLK_TOP_A_TUNER_SEL		56
#define CLK_TOP_U2U3_SEL		57
#define CLK_TOP_U2U3_SYS_SEL		58
#define CLK_TOP_U2U3_XHCI_SEL		59
#define CLK_TOP_DA_U2_REFSEL		60
#define CLK_TOP_DA_U2_CK_1P_SEL		61
#define CLK_TOP_AP2CNN_HOST_SEL		62
#define CLK_TOP_JTAG			63

/* INFRACFG */

#define CLK_INFRA_SYSAXI_D2		0
#define CLK_INFRA_UART0_SEL		1
#define CLK_INFRA_UART1_SEL		2
#define CLK_INFRA_UART2_SEL		3
#define CLK_INFRA_SPI0_SEL		4
#define CLK_INFRA_SPI1_SEL		5
#define CLK_INFRA_PWM1_SEL		6

Annotation

Implementation Notes