include/dt-bindings/clock/mt8135-clk.h
Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/mt8135-clk.h
File Facts
- System
- Linux kernel
- Corpus path
include/dt-bindings/clock/mt8135-clk.h- Extension
.h- Size
- 5246 bytes
- Lines
- 187
- Domain
- Repository Root And Misc
- Bucket
- include
- Inferred role
- Repository Root And Misc: implementation source
- Status
- source implementation candidate
Why This File Exists
Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
- Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _DT_BINDINGS_CLK_MT8135_H
#define _DT_BINDINGS_CLK_MT8135_H
/* TOPCKGEN */
#define CLK_TOP_DSI0_LNTC_DSICLK 1
#define CLK_TOP_HDMITX_CLKDIG_CTS 2
#define CLK_TOP_CLKPH_MCK 3
#define CLK_TOP_CPUM_TCK_IN 4
#define CLK_TOP_MAINPLL_806M 5
#define CLK_TOP_MAINPLL_537P3M 6
#define CLK_TOP_MAINPLL_322P4M 7
#define CLK_TOP_MAINPLL_230P3M 8
#define CLK_TOP_UNIVPLL_624M 9
#define CLK_TOP_UNIVPLL_416M 10
#define CLK_TOP_UNIVPLL_249P6M 11
#define CLK_TOP_UNIVPLL_178P3M 12
#define CLK_TOP_UNIVPLL_48M 13
#define CLK_TOP_MMPLL_D2 14
#define CLK_TOP_MMPLL_D3 15
#define CLK_TOP_MMPLL_D5 16
#define CLK_TOP_MMPLL_D7 17
#define CLK_TOP_MMPLL_D4 18
#define CLK_TOP_MMPLL_D6 19
#define CLK_TOP_SYSPLL_D2 20
#define CLK_TOP_SYSPLL_D4 21
#define CLK_TOP_SYSPLL_D6 22
#define CLK_TOP_SYSPLL_D8 23
#define CLK_TOP_SYSPLL_D10 24
#define CLK_TOP_SYSPLL_D12 25
#define CLK_TOP_SYSPLL_D16 26
#define CLK_TOP_SYSPLL_D24 27
#define CLK_TOP_SYSPLL_D3 28
#define CLK_TOP_SYSPLL_D2P5 29
#define CLK_TOP_SYSPLL_D5 30
#define CLK_TOP_SYSPLL_D3P5 31
#define CLK_TOP_UNIVPLL1_D2 32
#define CLK_TOP_UNIVPLL1_D4 33
#define CLK_TOP_UNIVPLL1_D6 34
#define CLK_TOP_UNIVPLL1_D8 35
#define CLK_TOP_UNIVPLL1_D10 36
#define CLK_TOP_UNIVPLL2_D2 37
#define CLK_TOP_UNIVPLL2_D4 38
#define CLK_TOP_UNIVPLL2_D6 39
#define CLK_TOP_UNIVPLL2_D8 40
#define CLK_TOP_UNIVPLL_D3 41
#define CLK_TOP_UNIVPLL_D5 42
#define CLK_TOP_UNIVPLL_D7 43
#define CLK_TOP_UNIVPLL_D10 44
#define CLK_TOP_UNIVPLL_D26 45
#define CLK_TOP_APLL 46
#define CLK_TOP_APLL_D4 47
#define CLK_TOP_APLL_D8 48
#define CLK_TOP_APLL_D16 49
#define CLK_TOP_APLL_D24 50
#define CLK_TOP_LVDSPLL_D2 51
#define CLK_TOP_LVDSPLL_D4 52
#define CLK_TOP_LVDSPLL_D8 53
#define CLK_TOP_LVDSTX_CLKDIG_CT 54
#define CLK_TOP_VPLL_DPIX 55
#define CLK_TOP_TVHDMI_H 56
#define CLK_TOP_HDMITX_CLKDIG_D2 57
#define CLK_TOP_HDMITX_CLKDIG_D3 58
#define CLK_TOP_TVHDMI_D2 59
#define CLK_TOP_TVHDMI_D4 60
#define CLK_TOP_MEMPLL_MCK_D4 61
#define CLK_TOP_AXI_SEL 62
#define CLK_TOP_SMI_SEL 63
#define CLK_TOP_MFG_SEL 64
#define CLK_TOP_IRDA_SEL 65
#define CLK_TOP_CAM_SEL 66
#define CLK_TOP_AUD_INTBUS_SEL 67
#define CLK_TOP_JPG_SEL 68
#define CLK_TOP_DISP_SEL 69
#define CLK_TOP_MSDC30_1_SEL 70
#define CLK_TOP_MSDC30_2_SEL 71
#define CLK_TOP_MSDC30_3_SEL 72
#define CLK_TOP_MSDC30_4_SEL 73
#define CLK_TOP_USB20_SEL 74
#define CLK_TOP_VENC_SEL 75
#define CLK_TOP_SPI_SEL 76
#define CLK_TOP_UART_SEL 77
#define CLK_TOP_MEM_SEL 78
#define CLK_TOP_CAMTG_SEL 79
#define CLK_TOP_AUDIO_SEL 80
#define CLK_TOP_FIX_SEL 81
#define CLK_TOP_VDEC_SEL 82
#define CLK_TOP_DDRPHYCFG_SEL 83
#define CLK_TOP_DPILVDS_SEL 84
#define CLK_TOP_PMICSPI_SEL 85
Annotation
- Atlas domain: Repository Root And Misc / include.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.