include/dt-bindings/clock/mt8516-clk.h
Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/mt8516-clk.h
File Facts
- System
- Linux kernel
- Corpus path
include/dt-bindings/clock/mt8516-clk.h- Extension
.h- Size
- 6623 bytes
- Lines
- 229
- Domain
- Repository Root And Misc
- Bucket
- include
- Inferred role
- Repository Root And Misc: implementation source
- Status
- source implementation candidate
Why This File Exists
Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
- Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _DT_BINDINGS_CLK_MT8516_H
#define _DT_BINDINGS_CLK_MT8516_H
/* APMIXEDSYS */
#define CLK_APMIXED_ARMPLL 0
#define CLK_APMIXED_MAINPLL 1
#define CLK_APMIXED_UNIVPLL 2
#define CLK_APMIXED_MMPLL 3
#define CLK_APMIXED_APLL1 4
#define CLK_APMIXED_APLL2 5
#define CLK_APMIXED_NR_CLK 6
/* INFRACFG */
#define CLK_IFR_MUX1_SEL 0
#define CLK_IFR_ETH_25M_SEL 1
#define CLK_IFR_I2C0_SEL 2
#define CLK_IFR_I2C1_SEL 3
#define CLK_IFR_I2C2_SEL 4
#define CLK_IFR_NR_CLK 5
/* TOPCKGEN */
#define CLK_TOP_CLK_NULL 0
#define CLK_TOP_I2S_INFRA_BCK 1
#define CLK_TOP_MEMPLL 2
#define CLK_TOP_DMPLL 3
#define CLK_TOP_MAINPLL_D2 4
#define CLK_TOP_MAINPLL_D4 5
#define CLK_TOP_MAINPLL_D8 6
#define CLK_TOP_MAINPLL_D16 7
#define CLK_TOP_MAINPLL_D11 8
#define CLK_TOP_MAINPLL_D22 9
#define CLK_TOP_MAINPLL_D3 10
#define CLK_TOP_MAINPLL_D6 11
#define CLK_TOP_MAINPLL_D12 12
#define CLK_TOP_MAINPLL_D5 13
#define CLK_TOP_MAINPLL_D10 14
#define CLK_TOP_MAINPLL_D20 15
#define CLK_TOP_MAINPLL_D40 16
#define CLK_TOP_MAINPLL_D7 17
#define CLK_TOP_MAINPLL_D14 18
#define CLK_TOP_UNIVPLL_D2 19
#define CLK_TOP_UNIVPLL_D4 20
#define CLK_TOP_UNIVPLL_D8 21
#define CLK_TOP_UNIVPLL_D16 22
#define CLK_TOP_UNIVPLL_D3 23
#define CLK_TOP_UNIVPLL_D6 24
#define CLK_TOP_UNIVPLL_D12 25
#define CLK_TOP_UNIVPLL_D24 26
#define CLK_TOP_UNIVPLL_D5 27
#define CLK_TOP_UNIVPLL_D20 28
#define CLK_TOP_MMPLL380M 29
#define CLK_TOP_MMPLL_D2 30
#define CLK_TOP_MMPLL_200M 31
#define CLK_TOP_USB_PHY48M 32
#define CLK_TOP_APLL1 33
#define CLK_TOP_APLL1_D2 34
#define CLK_TOP_APLL1_D4 35
#define CLK_TOP_APLL1_D8 36
#define CLK_TOP_APLL2 37
#define CLK_TOP_APLL2_D2 38
#define CLK_TOP_APLL2_D4 39
#define CLK_TOP_APLL2_D8 40
#define CLK_TOP_CLK26M 41
#define CLK_TOP_CLK26M_D2 42
#define CLK_TOP_AHB_INFRA_D2 43
#define CLK_TOP_NFI1X 44
#define CLK_TOP_ETH_D2 45
#define CLK_TOP_THEM 46
#define CLK_TOP_APDMA 47
#define CLK_TOP_I2C0 48
#define CLK_TOP_I2C1 49
#define CLK_TOP_AUXADC1 50
#define CLK_TOP_NFI 51
#define CLK_TOP_NFIECC 52
#define CLK_TOP_DEBUGSYS 53
#define CLK_TOP_PWM 54
#define CLK_TOP_UART0 55
#define CLK_TOP_UART1 56
#define CLK_TOP_BTIF 57
#define CLK_TOP_USB 58
#define CLK_TOP_FLASHIF_26M 59
#define CLK_TOP_AUXADC2 60
#define CLK_TOP_I2C2 61
#define CLK_TOP_MSDC0 62
#define CLK_TOP_MSDC1 63
#define CLK_TOP_NFI2X 64
#define CLK_TOP_PMICWRAP_AP 65
Annotation
- Atlas domain: Repository Root And Misc / include.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.