include/dt-bindings/clock/nuvoton,ma35d1-clk.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/nuvoton,ma35d1-clk.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/nuvoton,ma35d1-clk.h
Extension
.h
Size
5498 bytes
Lines
254
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H
#define __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H

/* external and internal oscillator clocks */
#define HXT		0
#define HXT_GATE	1
#define LXT		2
#define LXT_GATE	3
#define HIRC		4
#define HIRC_GATE	5
#define LIRC		6
#define LIRC_GATE	7
/* PLLs */
#define CAPLL		8
#define SYSPLL		9
#define DDRPLL		10
#define APLL		11
#define EPLL		12
#define VPLL		13
/* EPLL divider */
#define EPLL_DIV2	14
#define EPLL_DIV4	15
#define EPLL_DIV8	16
/* CPU clock, system clock, AXI, HCLK and PCLK */
#define CA35CLK_MUX	17
#define AXICLK_DIV2	18
#define AXICLK_DIV4	19
#define AXICLK_MUX	20
#define SYSCLK0_MUX	21
#define SYSCLK1_MUX	22
#define SYSCLK1_DIV2	23
#define HCLK0		24
#define HCLK1		25
#define HCLK2		26
#define PCLK0		27
#define PCLK1		28
#define PCLK2		29
#define HCLK3		30
#define PCLK3		31
#define PCLK4		32
/* AXI and AHB peripheral clocks */
#define USBPHY0		33
#define USBPHY1		34
#define DDR0_GATE	35
#define DDR6_GATE	36
#define CAN0_MUX	37
#define CAN0_DIV	38
#define CAN0_GATE	39
#define CAN1_MUX	40
#define CAN1_DIV	41
#define CAN1_GATE	42
#define CAN2_MUX	43
#define CAN2_DIV	44
#define CAN2_GATE	45
#define CAN3_MUX	46
#define CAN3_DIV	47
#define CAN3_GATE	48
#define SDH0_MUX	49
#define SDH0_GATE	50
#define SDH1_MUX	51
#define SDH1_GATE	52
#define NAND_GATE	53
#define USBD_GATE	54
#define USBH_GATE	55
#define HUSBH0_GATE	56
#define HUSBH1_GATE	57
#define GFX_MUX		58
#define GFX_GATE	59
#define VC8K_GATE	60
#define DCU_MUX		61
#define DCU_GATE	62
#define DCUP_DIV	63
#define EMAC0_GATE	64
#define EMAC1_GATE	65
#define CCAP0_MUX	66
#define CCAP0_DIV	67
#define CCAP0_GATE	68
#define CCAP1_MUX	69
#define CCAP1_DIV	70
#define CCAP1_GATE	71
#define PDMA0_GATE	72
#define PDMA1_GATE	73
#define PDMA2_GATE	74
#define PDMA3_GATE	75
#define WH0_GATE	76
#define WH1_GATE	77
#define HWS_GATE	78
#define EBI_GATE	79
#define SRAM0_GATE	80
#define SRAM1_GATE	81

Annotation

Implementation Notes