include/dt-bindings/clock/nvidia,tegra264.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/nvidia,tegra264.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/nvidia,tegra264.h
Extension
.h
Size
18096 bytes
Lines
467
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef DT_BINDINGS_CLOCK_NVIDIA_TEGRA264_H
#define DT_BINDINGS_CLOCK_NVIDIA_TEGRA264_H

#define TEGRA264_CLK_OSC				1
#define TEGRA264_CLK_CLK_S				2
#define TEGRA264_CLK_JTAG_REG				3
#define TEGRA264_CLK_SPLL				4
#define TEGRA264_CLK_SPLL_OUT0				5
#define TEGRA264_CLK_SPLL_OUT1				6
#define TEGRA264_CLK_SPLL_OUT2				7
#define TEGRA264_CLK_SPLL_OUT3				8
#define TEGRA264_CLK_SPLL_OUT4				9
#define TEGRA264_CLK_SPLL_OUT5				10
#define TEGRA264_CLK_SPLL_OUT6				11
#define TEGRA264_CLK_SPLL_OUT7				12
#define TEGRA264_CLK_AON_I2C				13
#define TEGRA264_CLK_HOST1X				14
#define TEGRA264_CLK_ISP				15
#define TEGRA264_CLK_ISP1				16
#define TEGRA264_CLK_ISP_ROOT				17
#define TEGRA264_CLK_NAFLL_PVA0_CORE			18
#define TEGRA264_CLK_NAFLL_PVA0_VPS			19
#define TEGRA264_CLK_NVCSI				20
#define TEGRA264_CLK_NVCSILP				21
#define TEGRA264_CLK_PLLP_OUT0				22
#define TEGRA264_CLK_PVA0_CPU_AXI			23
#define TEGRA264_CLK_PVA0_VPS				24
#define TEGRA264_CLK_PWM10				25
#define TEGRA264_CLK_PWM2				26
#define TEGRA264_CLK_PWM3				27
#define TEGRA264_CLK_PWM4				28
#define TEGRA264_CLK_PWM5				29
#define TEGRA264_CLK_PWM9				30
#define TEGRA264_CLK_QSPI0				31
#define TEGRA264_CLK_QSPI0_2X_PM			32
#define TEGRA264_CLK_RCE1_CPU				33
#define TEGRA264_CLK_RCE1_NIC				34
#define TEGRA264_CLK_RCE_CPU				35
#define TEGRA264_CLK_RCE_NIC				36
#define TEGRA264_CLK_SE					37
#define TEGRA264_CLK_SEU1				38
#define TEGRA264_CLK_SEU2				39
#define TEGRA264_CLK_SEU3				40
#define TEGRA264_CLK_SE_ROOT				41
#define TEGRA264_CLK_SPI1				42
#define TEGRA264_CLK_SPI2				43
#define TEGRA264_CLK_SPI3				44
#define TEGRA264_CLK_SPI4				45
#define TEGRA264_CLK_SPI5				46
#define TEGRA264_CLK_TOP_I2C				47
#define TEGRA264_CLK_TSEC				48
#define TEGRA264_CLK_TSEC_PKA				49
#define TEGRA264_CLK_UART0				50
#define TEGRA264_CLK_UART10				51
#define TEGRA264_CLK_UART11				52
#define TEGRA264_CLK_UART4				53
#define TEGRA264_CLK_UART5				54
#define TEGRA264_CLK_UART8				55
#define TEGRA264_CLK_UART9				56
#define TEGRA264_CLK_VI					57
#define TEGRA264_CLK_VI1				58
#define TEGRA264_CLK_VIC				59
#define TEGRA264_CLK_VI_ROOT				60
#define TEGRA264_CLK_DISPPLL				61
#define TEGRA264_CLK_SPPLL0				62
#define TEGRA264_CLK_SPPLL0_CLKOUT1A			63
#define TEGRA264_CLK_SPPLL0_CLKOUT2A			64
#define TEGRA264_CLK_SPPLL1				65
#define TEGRA264_CLK_VPLL0				66
#define TEGRA264_CLK_VPLL1				67
#define TEGRA264_CLK_VPLL2				68
#define TEGRA264_CLK_VPLL3				69
#define TEGRA264_CLK_VPLL4				70
#define TEGRA264_CLK_VPLL5				71
#define TEGRA264_CLK_VPLL6				72
#define TEGRA264_CLK_VPLL7				73
#define TEGRA264_CLK_RG0_DIV				74
#define TEGRA264_CLK_RG1_DIV				75
#define TEGRA264_CLK_RG2_DIV				76
#define TEGRA264_CLK_RG3_DIV				77
#define TEGRA264_CLK_RG4_DIV				78
#define TEGRA264_CLK_RG5_DIV				79
#define TEGRA264_CLK_RG6_DIV				80
#define TEGRA264_CLK_RG7_DIV				81
#define TEGRA264_CLK_RG0				82
#define TEGRA264_CLK_RG1				83
#define TEGRA264_CLK_RG2				84
#define TEGRA264_CLK_RG3				85
#define TEGRA264_CLK_RG4				86
#define TEGRA264_CLK_RG5				87

Annotation

Implementation Notes