include/dt-bindings/clock/px30-cru.h
Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/px30-cru.h
File Facts
- System
- Linux kernel
- Corpus path
include/dt-bindings/clock/px30-cru.h- Extension
.h- Size
- 9067 bytes
- Lines
- 388
- Domain
- Repository Root And Misc
- Bucket
- include
- Inferred role
- Repository Root And Misc: implementation source
- Status
- source implementation candidate
Why This File Exists
Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
- Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
#define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
/* core clocks */
#define PLL_APLL 1
#define PLL_DPLL 2
#define PLL_CPLL 3
#define PLL_NPLL 4
#define APLL_BOOST_H 5
#define APLL_BOOST_L 6
#define ARMCLK 7
/* sclk gates (special clocks) */
#define USB480M 14
#define SCLK_PDM 15
#define SCLK_I2S0_TX 16
#define SCLK_I2S0_TX_OUT 17
#define SCLK_I2S0_RX 18
#define SCLK_I2S0_RX_OUT 19
#define SCLK_I2S1 20
#define SCLK_I2S1_OUT 21
#define SCLK_I2S2 22
#define SCLK_I2S2_OUT 23
#define SCLK_UART1 24
#define SCLK_UART2 25
#define SCLK_UART3 26
#define SCLK_UART4 27
#define SCLK_UART5 28
#define SCLK_I2C0 29
#define SCLK_I2C1 30
#define SCLK_I2C2 31
#define SCLK_I2C3 32
#define SCLK_I2C4 33
#define SCLK_PWM0 34
#define SCLK_PWM1 35
#define SCLK_SPI0 36
#define SCLK_SPI1 37
#define SCLK_TIMER0 38
#define SCLK_TIMER1 39
#define SCLK_TIMER2 40
#define SCLK_TIMER3 41
#define SCLK_TIMER4 42
#define SCLK_TIMER5 43
#define SCLK_TSADC 44
#define SCLK_SARADC 45
#define SCLK_OTP 46
#define SCLK_OTP_USR 47
#define SCLK_CRYPTO 48
#define SCLK_CRYPTO_APK 49
#define SCLK_DDRC 50
#define SCLK_ISP 51
#define SCLK_CIF_OUT 52
#define SCLK_RGA_CORE 53
#define SCLK_VOPB_PWM 54
#define SCLK_NANDC 55
#define SCLK_SDIO 56
#define SCLK_EMMC 57
#define SCLK_SFC 58
#define SCLK_SDMMC 59
#define SCLK_OTG_ADP 60
#define SCLK_GMAC_SRC 61
#define SCLK_GMAC 62
#define SCLK_GMAC_RX_TX 63
#define SCLK_MAC_REF 64
#define SCLK_MAC_REFOUT 65
#define SCLK_MAC_OUT 66
#define SCLK_SDMMC_DRV 67
#define SCLK_SDMMC_SAMPLE 68
#define SCLK_SDIO_DRV 69
#define SCLK_SDIO_SAMPLE 70
#define SCLK_EMMC_DRV 71
#define SCLK_EMMC_SAMPLE 72
#define SCLK_GPU 73
#define SCLK_PVTM 74
#define SCLK_CORE_VPU 75
#define SCLK_GMAC_RMII 76
#define SCLK_UART2_SRC 77
#define SCLK_NANDC_DIV 78
#define SCLK_NANDC_DIV50 79
#define SCLK_SDIO_DIV 80
#define SCLK_SDIO_DIV50 81
#define SCLK_EMMC_DIV 82
#define SCLK_EMMC_DIV50 83
#define SCLK_DDRCLK 84
#define SCLK_UART1_SRC 85
#define SCLK_SDMMC_DIV 86
#define SCLK_SDMMC_DIV50 87
/* dclk gates */
#define DCLK_VOPB 150
Annotation
- Atlas domain: Repository Root And Misc / include.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.