include/dt-bindings/clock/qcom,eliza-gcc.h

Source file repositories/reference/linux-study-clean/include/dt-bindings/clock/qcom,eliza-gcc.h

File Facts

System
Linux kernel
Corpus path
include/dt-bindings/clock/qcom,eliza-gcc.h
Extension
.h
Size
7691 bytes
Lines
211
Domain
Repository Root And Misc
Bucket
include
Inferred role
Repository Root And Misc: implementation source
Status
source implementation candidate

Why This File Exists

Top-level or miscellaneous repository surface. Use this as map coverage unless a later manual pass promotes the file into a deeper subsystem dossier.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _DT_BINDINGS_CLK_QCOM_GCC_ELIZA_H
#define _DT_BINDINGS_CLK_QCOM_GCC_ELIZA_H

/* GCC clocks */
#define GCC_AGGRE_NOC_PCIE_AXI_CLK				0
#define GCC_AGGRE_UFS_PHY_AXI_CLK				1
#define GCC_AGGRE_USB3_PRIM_AXI_CLK				2
#define GCC_BOOT_ROM_AHB_CLK					3
#define GCC_CAM_BIST_MCLK_AHB_CLK				4
#define GCC_CAMERA_AHB_CLK					5
#define GCC_CAMERA_HF_AXI_CLK					6
#define GCC_CAMERA_SF_AXI_CLK					7
#define GCC_CAMERA_XO_CLK					8
#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK				9
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				10
#define GCC_CNOC_PCIE_SF_AXI_CLK				11
#define GCC_DDRSS_GPU_AXI_CLK					12
#define GCC_DDRSS_PCIE_SF_QTB_CLK				13
#define GCC_DISP_AHB_CLK					14
#define GCC_DISP_HF_AXI_CLK					15
#define GCC_GP1_CLK						16
#define GCC_GP1_CLK_SRC						17
#define GCC_GP2_CLK						18
#define GCC_GP2_CLK_SRC						19
#define GCC_GP3_CLK						20
#define GCC_GP3_CLK_SRC						21
#define GCC_GPLL0						22
#define GCC_GPLL0_OUT_EVEN					23
#define GCC_GPLL4						24
#define GCC_GPLL7						25
#define GCC_GPLL8						26
#define GCC_GPLL9						27
#define GCC_GPU_CFG_AHB_CLK					28
#define GCC_GPU_GEMNOC_GFX_CLK					29
#define GCC_GPU_GPLL0_CPH_CLK_SRC				30
#define GCC_GPU_GPLL0_DIV_CPH_CLK_SRC				31
#define GCC_GPU_SMMU_VOTE_CLK					32
#define GCC_MMU_TCU_VOTE_CLK					33
#define GCC_PCIE_0_AUX_CLK					34
#define GCC_PCIE_0_AUX_CLK_SRC					35
#define GCC_PCIE_0_CFG_AHB_CLK					36
#define GCC_PCIE_0_MSTR_AXI_CLK					37
#define GCC_PCIE_0_PHY_RCHNG_CLK				38
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC				39
#define GCC_PCIE_0_PIPE_CLK					40
#define GCC_PCIE_0_PIPE_CLK_SRC					41
#define GCC_PCIE_0_PIPE_DIV2_CLK				42
#define GCC_PCIE_0_PIPE_DIV2_CLK_SRC				43
#define GCC_PCIE_0_SLV_AXI_CLK					44
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				45
#define GCC_PCIE_1_AUX_CLK					46
#define GCC_PCIE_1_AUX_CLK_SRC					47
#define GCC_PCIE_1_CFG_AHB_CLK					48
#define GCC_PCIE_1_MSTR_AXI_CLK					49
#define GCC_PCIE_1_PHY_RCHNG_CLK				50
#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC				51
#define GCC_PCIE_1_PIPE_CLK					52
#define GCC_PCIE_1_PIPE_CLK_SRC					53
#define GCC_PCIE_1_PIPE_DIV2_CLK				54
#define GCC_PCIE_1_PIPE_DIV2_CLK_SRC				55
#define GCC_PCIE_1_SLV_AXI_CLK					56
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				57
#define GCC_PCIE_RSCC_CFG_AHB_CLK				58
#define GCC_PCIE_RSCC_XO_CLK					59
#define GCC_PDM2_CLK						60
#define GCC_PDM2_CLK_SRC					61
#define GCC_PDM_AHB_CLK						62
#define GCC_PDM_XO4_CLK						63
#define GCC_QMIP_CAMERA_CMD_AHB_CLK				64
#define GCC_QMIP_CAMERA_NRT_AHB_CLK				65
#define GCC_QMIP_CAMERA_RT_AHB_CLK				66
#define GCC_QMIP_GPU_AHB_CLK					67
#define GCC_QMIP_PCIE_AHB_CLK					68
#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK				69
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				70
#define GCC_QUPV3_WRAP1_CORE_2X_CLK				71
#define GCC_QUPV3_WRAP1_CORE_CLK				72
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK				73
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC			74
#define GCC_QUPV3_WRAP1_S0_CLK					75
#define GCC_QUPV3_WRAP1_S0_CLK_SRC				76
#define GCC_QUPV3_WRAP1_S1_CLK					77
#define GCC_QUPV3_WRAP1_S1_CLK_SRC				78
#define GCC_QUPV3_WRAP1_S2_CLK					79
#define GCC_QUPV3_WRAP1_S2_CLK_SRC				80
#define GCC_QUPV3_WRAP1_S3_CLK					81
#define GCC_QUPV3_WRAP1_S3_CLK_SRC				82
#define GCC_QUPV3_WRAP1_S4_CLK					83
#define GCC_QUPV3_WRAP1_S4_CLK_SRC				84
#define GCC_QUPV3_WRAP1_S5_CLK					85

Annotation

Implementation Notes